A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation.

S. Moreno Londono, J. Pineda de Gyvez

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

5 Citations (Scopus)

Abstract

Digital circuits have been traditionally designed to meet the worst PVT conditions to guarantee high yield. This design methodology produces an integrated circuit which has a big overhead in terms of area and power consumption in most of the cases. In this paper, a new better-than-worst-case-design methodology is proposed. It is based on a timing error speculation technique which features simple monitors located in the critical paths of the circuit that will speculate whether a timing error is going to occur or not. Using a 32-bit multiplier, this design methodology achieved area and power savings up to 50%, with 5 % performance loss.
Original languageEnglish
Title of host publicationProceedings of the 25th IEEE Systems-on-Chip Conference, SOCC 2012, 12-14 september 2012, Niagara Falls, New York
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages15-20
ISBN (Print)978-1-4673-1294-3
DOIs
Publication statusPublished - 2012
Eventconference; SOCC 2012, 12-14 September 2012, Niagara Falls, USA -
Duration: 1 Jan 2012 → …

Conference

Conferenceconference; SOCC 2012, 12-14 September 2012, Niagara Falls, USA
Period1/01/12 → …
OtherSOCC 2012, 12-14 September 2012, Niagara Falls, USA

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