A BDD-based verification method for large synthesized circuits

C.A.J. Eijk, van

Research output: Contribution to journalArticleAcademicpeer-review

2 Citations (Scopus)


Nowadays, logic synthesis tools are widely used to optimize and implement digital systems. Verifying the correctness of the generated circuits is an important practical problem. We present a new formal verification method for large synthesized circuits. It combines the use of binary decision diagrams (BDDs) with techniques to exploit the structural similarities of the circuits under comparison. These similarities are detected automatically. We show that the proposed method significantly extends the capability of BDD-based methods to verify large synthesized circuits.
Original languageEnglish
Pages (from-to)131-149
Number of pages19
JournalIntegration : the VLSI Journal
Issue number2
Publication statusPublished - 1997


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