A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-reset

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Abstract

In this work, a novel DAC reset scheme for SAR ADCs is proposed, which eliminates the reset energy consumption. This reset energy consumption can be significant and is seldom optimized in low power switching schemes. The scheme can be applied to all differentially reset and switched DACs. This `swap-to-reset' operation is applied to the 2 MSBs of a 12b SAR ADC fabricated in 65nm CMOS, resulting in an energy saving of 33% for the DAC or 18% for the whole ADC. Besides swapping, rotation is also applied to the 2 MSBs of the DAC to enhance the linearity to 88dB SFDR. The SAR ADC operates at 0.8V VDD and 40kS/s, achieving an SNDR of 64.2dB and a FoM of 7.1fJ/conversion-step.
Original languageEnglish
Title of host publicationEuropean Solid-State Circuits Conference, ESSCIRC Conference 2016: 42nd
PublisherInstitute of Electrical and Electronics Engineers
Pages409-412
ISBN (Electronic)978-1-5090-2972-3
ISBN (Print)978-1-5090-2973-0
DOIs
Publication statusPublished - 2016
Event42th European Solid-State Circuits Conference (ESSCIRC 2016) - Lausanne, Switzerland
Duration: 12 Sep 201615 Dec 2016
Conference number: 42

Conference

Conference42th European Solid-State Circuits Conference (ESSCIRC 2016)
Abbreviated titleESSCIRC2016
CountrySwitzerland
CityLausanne
Period12/09/1615/12/16
OtherESSCIRC 2016 is sometimes 42th and sometimes 46th

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Cite this

Liu, M., van Roermund, A. H. M., & Harpe, P. J. A. (2016). A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-reset. In European Solid-State Circuits Conference, ESSCIRC Conference 2016: 42nd (pp. 409-412). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIRC.2016.7598328