A 71 GHz 3-Stage Rectifier with 8% Efficiency

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Abstract

This paper presents a 71 GHz fully on-chip 3-stage inductor-peaked rectifier in 65-nm CMOS technology. The multistage rectifier is the bottleneck in realizing on-chip wireless power receivers. In this paper, sensitivity and efficiency problems of the mm-wave rectifier are discussed and a 3-stage inductor-peaked rectifier structure is proposed and realized. By cascading inductor-peaked rectifiers with optimized layout, the measured rectifier provide 1 V output voltage with 5 dBm input power at 71 GHz, it also reaches 8% efficiency with 720 μA current load. Compared to previous work of 45 GHz rectifier with 1.2% efficiency [1] and 62 GHz with 7% efficiency [2], this work provides higher efficiency and higher output voltage for mm-wave wireless power receivers.

Original languageEnglish
Title of host publication2019 IEEE MTT-S International Wireless Symposium, IWS 2019 - Proceedings
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages3
ISBN (Electronic)9781728107165
DOIs
Publication statusPublished - 1 May 2019
Event6th IEEE MTT-S International Wireless Symposium - Guangzhou, China
Duration: 19 May 201922 May 2019
https://10times.com/ieee-iws

Conference

Conference6th IEEE MTT-S International Wireless Symposium
Abbreviated titleIEEE IWS 2019
CountryChina
CityGuangzhou
Period19/05/1922/05/19
Internet address

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Cite this

Gao, H., & Baltus, P. (2019). A 71 GHz 3-Stage Rectifier with 8% Efficiency. In 2019 IEEE MTT-S International Wireless Symposium, IWS 2019 - Proceedings [8804129] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/IEEE-IWS.2019.8804129