Abstract
This paper presents a 71 GHz fully on-chip 3-stage inductor-peaked rectifier in 65-nm CMOS technology. The multistage rectifier is the bottleneck in realizing on-chip wireless power receivers. In this paper, sensitivity and efficiency problems of the mm-wave rectifier are discussed and a 3-stage inductor-peaked rectifier structure is proposed and realized. By cascading inductor-peaked rectifiers with optimized layout, the measured rectifier provide 1 V output voltage with 5 dBm input power at 71 GHz, it also reaches 8% efficiency with 720 μA current load. Compared to previous work of 45 GHz rectifier with 1.2% efficiency [1] and 62 GHz with 7% efficiency [2], this work provides higher efficiency and higher output voltage for mm-wave wireless power receivers.
| Original language | English |
|---|---|
| Title of host publication | 2019 IEEE MTT-S International Wireless Symposium, IWS 2019 - Proceedings |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Number of pages | 3 |
| ISBN (Electronic) | 9781728107165 |
| DOIs | |
| Publication status | Published - 1 May 2019 |
| Event | 6th IEEE MTT-S International Wireless Symposium - Guangzhou, China Duration: 19 May 2019 → 22 May 2019 https://10times.com/ieee-iws |
Conference
| Conference | 6th IEEE MTT-S International Wireless Symposium |
|---|---|
| Abbreviated title | IEEE IWS 2019 |
| Country | China |
| City | Guangzhou |
| Period | 19/05/19 → 22/05/19 |
| Internet address |
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A 71 GHz 3-Stage Rectifier with 8% Efficiency. / Gao, Hao; Baltus, Peter.
2019 IEEE MTT-S International Wireless Symposium, IWS 2019 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2019. 8804129.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - A 71 GHz 3-Stage Rectifier with 8% Efficiency
AU - Gao, Hao
AU - Baltus, Peter
PY - 2019/5/1
Y1 - 2019/5/1
N2 - This paper presents a 71 GHz fully on-chip 3-stage inductor-peaked rectifier in 65-nm CMOS technology. The multistage rectifier is the bottleneck in realizing on-chip wireless power receivers. In this paper, sensitivity and efficiency problems of the mm-wave rectifier are discussed and a 3-stage inductor-peaked rectifier structure is proposed and realized. By cascading inductor-peaked rectifiers with optimized layout, the measured rectifier provide 1 V output voltage with 5 dBm input power at 71 GHz, it also reaches 8% efficiency with 720 μA current load. Compared to previous work of 45 GHz rectifier with 1.2% efficiency [1] and 62 GHz with 7% efficiency [2], this work provides higher efficiency and higher output voltage for mm-wave wireless power receivers.
AB - This paper presents a 71 GHz fully on-chip 3-stage inductor-peaked rectifier in 65-nm CMOS technology. The multistage rectifier is the bottleneck in realizing on-chip wireless power receivers. In this paper, sensitivity and efficiency problems of the mm-wave rectifier are discussed and a 3-stage inductor-peaked rectifier structure is proposed and realized. By cascading inductor-peaked rectifiers with optimized layout, the measured rectifier provide 1 V output voltage with 5 dBm input power at 71 GHz, it also reaches 8% efficiency with 720 μA current load. Compared to previous work of 45 GHz rectifier with 1.2% efficiency [1] and 62 GHz with 7% efficiency [2], this work provides higher efficiency and higher output voltage for mm-wave wireless power receivers.
UR - http://www.scopus.com/inward/record.url?scp=85071727184&partnerID=8YFLogxK
U2 - 10.1109/IEEE-IWS.2019.8804129
DO - 10.1109/IEEE-IWS.2019.8804129
M3 - Conference contribution
AN - SCOPUS:85071727184
BT - 2019 IEEE MTT-S International Wireless Symposium, IWS 2019 - Proceedings
PB - Institute of Electrical and Electronics Engineers
CY - Piscataway
ER -