A 7.1-fJ/conversion-step 88-dB SFDR SAR ADC with energy-free "swap to reset"

M. Liu, A.H.M. van Roermund, P. Harpe

Research output: Contribution to journalArticleAcademicpeer-review

15 Citations (Scopus)
152 Downloads (Pure)


The digital-to-analog converter (DAC) in SAR anolog-to-digital converters (ADCs) is often dominant for both power consumption and linearity. Dedicated switching schemes can save power, but mostly focus on conversion energy, whereas the DAC reset can consume significant energy as well. This paper presents an energy-free DAC reset scheme, 'swap to reset,' for charge-redistribution SAR ADCs. It is widely applicable to existing low-power switching schemes. Additionally, to limit complexity while maintaining most of the energy savings, it can be utilized for the MSBs of the DAC only while the LSBs use conventional reset. To demonstrate the scheme, it is applied to the 2 MSBs of a 12-b SAR ADC using a split-monotonic DAC in 65-nm CMOS, resulting in an energy saving of 33% for the DAC or 18% for the whole ADC. Besides the 'swap to reset,' a rotation is also applied to the 2 MSBs, hence enhancing the linearity to 88-dB spurious free dynamic range. The SAR ADC operates at 0.8-V power supply and 40 kS/s, achieving an signal to noise and distortion ratio of 64.2 dB and a Figure of Merit of 7.1-fJ/conversion step.

Original languageEnglish
Article number8038759
Pages (from-to)2979-2990
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Issue number11
Publication statusPublished - 1 Nov 2017


  • CMOS
  • energy efficiency
  • high linearity
  • reset energy
  • rotation
  • SAR anolog-to-digital converter (ADC)
  • swap to reset


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