A 70 Ms/s 110 mW 8-b CMOS folding and interpolating A/D converter

B. Nauta, A.G.W. Venes

    Research output: Contribution to journalArticleAcademicpeer-review

    88 Citations (Scopus)
    100 Downloads (Pure)

    Abstract

    A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm2 in 0.8 µm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW
    Original languageEnglish
    Pages (from-to)1302-1309
    Number of pages7
    JournalIEEE Journal of Solid-State Circuits
    Volume30
    Issue number12
    DOIs
    Publication statusPublished - 1995

    Fingerprint

    Networks (circuits)
    Ladders
    Digital to analog conversion
    Bandwidth
    Compensation and Redress

    Cite this

    Nauta, B. ; Venes, A.G.W. / A 70 Ms/s 110 mW 8-b CMOS folding and interpolating A/D converter. In: IEEE Journal of Solid-State Circuits. 1995 ; Vol. 30, No. 12. pp. 1302-1309.
    @article{bb2b4ac2aa4146eb82c5ddf063bd87d2,
    title = "A 70 Ms/s 110 mW 8-b CMOS folding and interpolating A/D converter",
    abstract = "A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm2 in 0.8 µm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW",
    author = "B. Nauta and A.G.W. Venes",
    year = "1995",
    doi = "10.1109/4.482155",
    language = "English",
    volume = "30",
    pages = "1302--1309",
    journal = "IEEE Journal of Solid-State Circuits",
    issn = "0018-9200",
    publisher = "Institute of Electrical and Electronics Engineers",
    number = "12",

    }

    A 70 Ms/s 110 mW 8-b CMOS folding and interpolating A/D converter. / Nauta, B.; Venes, A.G.W.

    In: IEEE Journal of Solid-State Circuits, Vol. 30, No. 12, 1995, p. 1302-1309.

    Research output: Contribution to journalArticleAcademicpeer-review

    TY - JOUR

    T1 - A 70 Ms/s 110 mW 8-b CMOS folding and interpolating A/D converter

    AU - Nauta, B.

    AU - Venes, A.G.W.

    PY - 1995

    Y1 - 1995

    N2 - A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm2 in 0.8 µm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW

    AB - A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm2 in 0.8 µm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW

    U2 - 10.1109/4.482155

    DO - 10.1109/4.482155

    M3 - Article

    VL - 30

    SP - 1302

    EP - 1309

    JO - IEEE Journal of Solid-State Circuits

    JF - IEEE Journal of Solid-State Circuits

    SN - 0018-9200

    IS - 12

    ER -