A 70 Ms/s 110 mW 8-b CMOS folding and interpolating A/D converter

B. Nauta, A.G.W. Venes

    Research output: Contribution to journalArticleAcademicpeer-review

    98 Citations (Scopus)
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    A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm2 in 0.8 µm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW
    Original languageEnglish
    Pages (from-to)1302-1309
    Number of pages7
    JournalIEEE Journal of Solid-State Circuits
    Issue number12
    Publication statusPublished - 1995


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