Applications like wireless sensor nodes require ultra-low-power ADCs. However, each application has different requirements for accuracy and bandwidth. Recent power-efficient ADCs for sensor applications are mostly designed for a fixed accuracy and a limited range of sample rates. An efficiently scalable sample rate (10kS/s to 10MS/s) has been demonstrated before, but without scalability of resolution. In, an ADC with both flexible resolution and sample rate is reported; however, its power efficiency is not as good as the point-solutions in. This paper describes a SAR ADC that achieves both good power efficiency (6.5-to-16fJ/conversion-step) and a wide range of flexibility (7-to-10b resolution, sample rates up to 4MS/s) to cover a large variety of applications, thereby reducing cost, design-time and overall complexity. To optimize the power efficiency for each resolution, both the DAC and comparator are reconfigurable. A 2-step conversion scheme is proposed for 9 and 10b settings to further reduce the power consumption. Finally, the use of an asynchronous architecture and dynamic circuitry ensures that the power consumption scales inherently proportional to the sample rate.
|Title of host publication||Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 19-23 February 2012, San Francisco, California|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2012|