A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS

C. Zhang; L. Breems; Qilong Liu; G. Radulov; M. Bolatkale; S. Bajoria; R. Rutten; A.H.M. Van Roermund

doi:10.1109/ESSCIRC53450.2021.9567777

A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS

C. Zhang
, L. Breems
, Qilong Liu
, G. Radulov
, M. Bolatkale
, S. Bajoria
, R. Rutten
, A.H.M. Van Roermund

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

12 Citations (Scopus)

Abstract

This paper presents a 6GS/s 0.5GHz bandwidth CT 2-1-1 MASH 3b ΔΣ modulator in 40nm CMOS. To enable the 0.5GHz bandwidth, the modulator employs current-mode excess loop delay compensation with phase boosting, current-mode locally-time-interleaved quantizers, and on-chip comparator offset calibration to realize high-speed ELD-compensated 3-bit quantizers. High sampling frequency, multi-bit quantization and multi-stage noise-shaping enable the ADC to achieve 58dB DR in 500MHz BW when sampled at 6GHz. If sampled at 4GHz, 65dB DR can be achieved at a BW of 300MHz.

Original language	English
Title of host publication	ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
Publisher	Institute of Electrical and Electronics Engineers
Pages	491-494
Number of pages	4
ISBN (Electronic)	978-1-6654-3751-6
DOIs	https://doi.org/10.1109/ESSCIRC53450.2021.9567777
Publication status	Published - 26 Oct 2021
Event	47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 - Virtual, Online, Grenoble, France Duration: 13 Sept 2021 → 22 Sept 2021 https://www.esscirc-essderc2021.org/

Conference

Conference	47th IEEE European Solid State Circuits Conference, ESSCIRC 2021
Country/Territory	France
City	Grenoble
Period	13/09/21 → 22/09/21
Internet address	https://www.esscirc-essderc2021.org/

Bibliographical note

Funding Information:
This work is supported by Dutch Technology Foundation STW (grant 12433) and by NXP Semiconductors, Eindhoven.

Funding

This work is supported by Dutch Technology Foundation STW (grant 12433) and by NXP Semiconductors, Eindhoven.

Keywords

comparator offset calibration
CT ΔΣ ADC
ELD compensation
MASH

Access to Document

10.1109/ESSCIRC53450.2021.9567777

Cite this

Zhang, C., Breems, L., Liu, Q., Radulov, G., Bolatkale, M., Bajoria, S., Rutten, R., & Van Roermund, A. H. M. (2021). A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC) (pp. 491-494). Article 9567777 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIRC53450.2021.9567777

@inproceedings{1bccb0763194428883c28648f8c1cc06,

title = "A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS",

abstract = "This paper presents a 6GS/s 0.5GHz bandwidth CT 2-1-1 MASH 3b ΔΣ modulator in 40nm CMOS. To enable the 0.5GHz bandwidth, the modulator employs current-mode excess loop delay compensation with phase boosting, current-mode locally-time-interleaved quantizers, and on-chip comparator offset calibration to realize high-speed ELD-compensated 3-bit quantizers. High sampling frequency, multi-bit quantization and multi-stage noise-shaping enable the ADC to achieve 58dB DR in 500MHz BW when sampled at 6GHz. If sampled at 4GHz, 65dB DR can be achieved at a BW of 300MHz. ",

keywords = "comparator offset calibration, CT \ΔΣ ADC, ELD compensation, MASH",

author = "C. Zhang and L. Breems and Qilong Liu and G. Radulov and M. Bolatkale and S. Bajoria and R. Rutten and \{Van Roermund\}, A.H.M.",

note = "Funding Information: This work is supported by Dutch Technology Foundation STW (grant 12433) and by NXP Semiconductors, Eindhoven. ; 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 ; Conference date: 13-09-2021 Through 22-09-2021",

year = "2021",

month = oct,

day = "26",

doi = "10.1109/ESSCIRC53450.2021.9567777",

language = "English",

pages = "491--494",

booktitle = "ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)",

publisher = "Institute of Electrical and Electronics Engineers",

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}

Zhang, C, Breems, L , Liu, Q , Radulov, G, Bolatkale, M, Bajoria, S, Rutten, R & Van Roermund, AHM 2021, A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS. in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)., 9567777, Institute of Electrical and Electronics Engineers, pp. 491-494, 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021, Grenoble, France, 13/09/21. https://doi.org/10.1109/ESSCIRC53450.2021.9567777

A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS. / Zhang, C.; Breems, L.; Liu, Qilong et al.
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC). Institute of Electrical and Electronics Engineers, 2021. p. 491-494 9567777.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS

AU - Zhang, C.

AU - Breems, L.

AU - Liu, Qilong

AU - Radulov, G.

AU - Bolatkale, M.

AU - Bajoria, S.

AU - Rutten, R.

AU - Van Roermund, A.H.M.

N1 - Funding Information: This work is supported by Dutch Technology Foundation STW (grant 12433) and by NXP Semiconductors, Eindhoven.

PY - 2021/10/26

Y1 - 2021/10/26

N2 - This paper presents a 6GS/s 0.5GHz bandwidth CT 2-1-1 MASH 3b ΔΣ modulator in 40nm CMOS. To enable the 0.5GHz bandwidth, the modulator employs current-mode excess loop delay compensation with phase boosting, current-mode locally-time-interleaved quantizers, and on-chip comparator offset calibration to realize high-speed ELD-compensated 3-bit quantizers. High sampling frequency, multi-bit quantization and multi-stage noise-shaping enable the ADC to achieve 58dB DR in 500MHz BW when sampled at 6GHz. If sampled at 4GHz, 65dB DR can be achieved at a BW of 300MHz.

AB - This paper presents a 6GS/s 0.5GHz bandwidth CT 2-1-1 MASH 3b ΔΣ modulator in 40nm CMOS. To enable the 0.5GHz bandwidth, the modulator employs current-mode excess loop delay compensation with phase boosting, current-mode locally-time-interleaved quantizers, and on-chip comparator offset calibration to realize high-speed ELD-compensated 3-bit quantizers. High sampling frequency, multi-bit quantization and multi-stage noise-shaping enable the ADC to achieve 58dB DR in 500MHz BW when sampled at 6GHz. If sampled at 4GHz, 65dB DR can be achieved at a BW of 300MHz.

KW - comparator offset calibration

KW - CT ΔΣ ADC

KW - ELD compensation

KW - MASH

UR - https://www.scopus.com/pages/publications/85118469112

U2 - 10.1109/ESSCIRC53450.2021.9567777

DO - 10.1109/ESSCIRC53450.2021.9567777

M3 - Conference contribution

AN - SCOPUS:85118469112

SP - 491

EP - 494

BT - ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)

PB - Institute of Electrical and Electronics Engineers

T2 - 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021

Y2 - 13 September 2021 through 22 September 2021

ER -

Zhang C, Breems L , Liu Q , Radulov G, Bolatkale M, Bajoria S et al. A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS. In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC). Institute of Electrical and Electronics Engineers. 2021. p. 491-494. 9567777 doi: 10.1109/ESSCIRC53450.2021.9567777

A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS

Abstract

Conference

Bibliographical note

Funding

Keywords

Access to Document

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