A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction

L. Yan; P.J.A. Harpe; M. Osawa; Y. Harada; K. Tamiya; C. Van Hoof; R.F. Yazicioglu

doi:10.1109/ISSCC.2014.6757495

A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction

L. Yan, P.J.A. Harpe, M. Osawa, Y. Harada, K. Tamiya, C. Van Hoof, R.F. Yazicioglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

32 Citations (SciVal)

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Abstract

Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1µW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.

Original language	English
Title of host publication	Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA
Editors	L.C. Fujino
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	418-419
ISBN (Print)	978-1-4799-0918-6
DOIs	https://doi.org/10.1109/ISSCC.2014.6757495
Publication status	Published - 2014
Event	61st IEEE International Solid-State Circuits Conference, ISSCC 2014 - San Francisco, United States Duration: 9 Feb 2014 → 13 Feb 2014 Conference number: 61

Conference

Conference	61st IEEE International Solid-State Circuits Conference, ISSCC 2014
Abbreviated title	ISSCC 2014
Country/Territory	United States
City	San Francisco
Period	9/02/14 → 13/02/14
Other	“Silicon Systems Bridging the Cloud”

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10.1109/ISSCC.2014.6757495

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Yan, L., Harpe, P. J. A., Osawa, M., Harada, Y., Tamiya, K., Van Hoof, C., & Yazicioglu, R. F. (2014). A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction. In L. C. Fujino (Ed.), Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA (pp. 418-419). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSCC.2014.6757495

Yan, L. ; Harpe, P.J.A. ; Osawa, M. et al. / A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction. Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA. editor / L.C. Fujino. Piscataway : Institute of Electrical and Electronics Engineers, 2014. pp. 418-419

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title = "A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction",

abstract = "Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1µW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.",

author = "L. Yan and P.J.A. Harpe and M. Osawa and Y. Harada and K. Tamiya and {Van Hoof}, C. and R.F. Yazicioglu",

year = "2014",

doi = "10.1109/ISSCC.2014.6757495",

language = "English",

isbn = "978-1-4799-0918-6",

pages = "418--419",

editor = "L.C. Fujino",

booktitle = "Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "61st IEEE International Solid-State Circuits Conference, ISSCC 2014, ISSCC 2014 ; Conference date: 09-02-2014 Through 13-02-2014",

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Yan, L, Harpe, PJA, Osawa, M, Harada, Y, Tamiya, K, Van Hoof, C & Yazicioglu, RF 2014, A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction. in LC Fujino (ed.), Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA. Institute of Electrical and Electronics Engineers, Piscataway, pp. 418-419, 61st IEEE International Solid-State Circuits Conference, ISSCC 2014, San Francisco, California, United States, 9/02/14. https://doi.org/10.1109/ISSCC.2014.6757495

A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction. / Yan, L.; Harpe, P.J.A.; Osawa, M. et al.
Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA. ed. / L.C. Fujino. Piscataway: Institute of Electrical and Electronics Engineers, 2014. p. 418-419.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction

AU - Yan, L.

AU - Harpe, P.J.A.

AU - Osawa, M.

AU - Harada, Y.

AU - Tamiya, K.

AU - Van Hoof, C.

AU - Yazicioglu, R.F.

N1 - Conference code: 61

PY - 2014

Y1 - 2014

N2 - Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1µW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.

AB - Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1µW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.

U2 - 10.1109/ISSCC.2014.6757495

DO - 10.1109/ISSCC.2014.6757495

M3 - Conference contribution

SN - 978-1-4799-0918-6

SP - 418

EP - 419

BT - Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA

A2 - Fujino, L.C.

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 61st IEEE International Solid-State Circuits Conference, ISSCC 2014

Y2 - 9 February 2014 through 13 February 2014

ER -

Yan L, Harpe PJA, Osawa M, Harada Y, Tamiya K, Van Hoof C et al. A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction. In Fujino LC, editor, Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA. Piscataway: Institute of Electrical and Electronics Engineers. 2014. p. 418-419 doi: 10.1109/ISSCC.2014.6757495

A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction

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