A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction

L. Yan, P.J.A. Harpe, M. Osawa, Y. Harada, K. Tamiya, C. Van Hoof, R.F. Yazicioglu

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

16 Citations (Scopus)
6 Downloads (Pure)

Abstract

Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1µW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.
Original languageEnglish
Title of host publicationProceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA
EditorsL.C. Fujino
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages418-419
ISBN (Print)978-1-4799-0918-6
DOIs
Publication statusPublished - 2014
Event2014 61st IEEE International Solid-State Circuits Conference (ISSCC 2014) - San Francisco, CA, United States
Duration: 9 Feb 201413 Feb 2014
Conference number: 61

Conference

Conference2014 61st IEEE International Solid-State Circuits Conference (ISSCC 2014)
Abbreviated titleISSCC 2014
CountryUnited States
CitySan Francisco, CA
Period9/02/1413/02/14
Other“Silicon Systems Bridging the Cloud”

Fingerprint

Electrocardiography
Feature extraction
Pacemakers
Electric power utilization
Parameter extraction
Computational complexity

Cite this

Yan, L., Harpe, P. J. A., Osawa, M., Harada, Y., Tamiya, K., Van Hoof, C., & Yazicioglu, R. F. (2014). A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction. In L. C. Fujino (Ed.), Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA (pp. 418-419). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSCC.2014.6757495
Yan, L. ; Harpe, P.J.A. ; Osawa, M. ; Harada, Y. ; Tamiya, K. ; Van Hoof, C. ; Yazicioglu, R.F. / A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction. Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA. editor / L.C. Fujino. Piscataway : Institute of Electrical and Electronics Engineers, 2014. pp. 418-419
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abstract = "Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1µW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.",
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Yan, L, Harpe, PJA, Osawa, M, Harada, Y, Tamiya, K, Van Hoof, C & Yazicioglu, RF 2014, A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction. in LC Fujino (ed.), Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA. Institute of Electrical and Electronics Engineers, Piscataway, pp. 418-419, 2014 61st IEEE International Solid-State Circuits Conference (ISSCC 2014), San Francisco, CA, United States, 9/02/14. https://doi.org/10.1109/ISSCC.2014.6757495

A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction. / Yan, L.; Harpe, P.J.A.; Osawa, M.; Harada, Y.; Tamiya, K.; Van Hoof, C.; Yazicioglu, R.F.

Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA. ed. / L.C. Fujino. Piscataway : Institute of Electrical and Electronics Engineers, 2014. p. 418-419.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction

AU - Yan, L.

AU - Harpe, P.J.A.

AU - Osawa, M.

AU - Harada, Y.

AU - Tamiya, K.

AU - Van Hoof, C.

AU - Yazicioglu, R.F.

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N2 - Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1µW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.

AB - Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1µW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.

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M3 - Conference contribution

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BT - Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA

A2 - Fujino, L.C.

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ER -

Yan L, Harpe PJA, Osawa M, Harada Y, Tamiya K, Van Hoof C et al. A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction. In Fujino LC, editor, Proceedings of the 2014 IEEE International Solid-State Circuits Conference (ISSCC) : digest of technical papers, 9-13 February 2014, San Francisco, USA. Piscataway: Institute of Electrical and Electronics Engineers. 2014. p. 418-419 https://doi.org/10.1109/ISSCC.2014.6757495