A 62dB SFDR, 500MSPS, 15mW open-loop track-and-hold circuit

P.J.A. Harpe; A. Zanikopoulos; J.A. Hegt; A.H.M. Roermund, van

doi:10.1109/NORCHP.2006.329254

A 62dB SFDR, 500MSPS, 15mW open-loop track-and-hold circuit

P.J.A. Harpe
, A. Zanikopoulos
, J.A. Hegt
, A.H.M. Roermund, van

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

11 Citations (Scopus)

Abstract

In this work, the design of an open-loop front-end track & hold (T&H) circuit is considered. Advantages of the presented circuit include low power-consumption, high-speed operation, simple reliable design, and ability to operate at low power-supplies. The major problem of open-loop circuits is their relatively poor linearity. In the presented design, high linearity is achieved by applying three linearization techniques: clock boosting (Abo and Gray, 1999), resistive source degeneration (Razavi, 2001), (Ouzounov et al., 2005) and cross-coupling (Ouzounov et al., 2005), (Voorman and Veenstra, 2000). As a result, a linearity corresponding to 10-bit accuracy is achieved. The final design in a 0.18mum CMOS process achieves an SFDR of 62 dB using a sample frequency of 500 MHz while consuming 15mW at a 1.8V power supply

Original language	English
Title of host publication	Proceedings of the 24th IEEE Norchip 2006 Conference
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	103-106
Number of pages	4
ISBN (Print)	1-4244-0772-9
DOIs	https://doi.org/10.1109/NORCHP.2006.329254
Publication status	Published - 2006
Event	IEEE Norchip 2006 - Linkoping, Sweden Duration: 20 Nov 2006 → 21 Nov 2006

Conference

Conference	IEEE Norchip 2006
Country/Territory	Sweden
City	Linkoping
Period	20/11/06 → 21/11/06

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10.1109/NORCHP.2006.329254

Cite this

@inproceedings{f6d5b44eae414d338dad6b9a905769d4,

title = "A 62dB SFDR, 500MSPS, 15mW open-loop track-and-hold circuit",

abstract = "In this work, the design of an open-loop front-end track \& hold (T\&H) circuit is considered. Advantages of the presented circuit include low power-consumption, high-speed operation, simple reliable design, and ability to operate at low power-supplies. The major problem of open-loop circuits is their relatively poor linearity. In the presented design, high linearity is achieved by applying three linearization techniques: clock boosting (Abo and Gray, 1999), resistive source degeneration (Razavi, 2001), (Ouzounov et al., 2005) and cross-coupling (Ouzounov et al., 2005), (Voorman and Veenstra, 2000). As a result, a linearity corresponding to 10-bit accuracy is achieved. The final design in a 0.18mum CMOS process achieves an SFDR of 62 dB using a sample frequency of 500 MHz while consuming 15mW at a 1.8V power supply",

author = "P.J.A. Harpe and A. Zanikopoulos and J.A. Hegt and \{Roermund, van\}, A.H.M.",

year = "2006",

doi = "10.1109/NORCHP.2006.329254",

language = "English",

isbn = "1-4244-0772-9",

pages = "103--106",

booktitle = "Proceedings of the 24th IEEE Norchip 2006 Conference",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "IEEE Norchip 2006 ; Conference date: 20-11-2006 Through 21-11-2006",

}

TY - GEN

T1 - A 62dB SFDR, 500MSPS, 15mW open-loop track-and-hold circuit

AU - Harpe, P.J.A.

AU - Zanikopoulos, A.

AU - Hegt, J.A.

AU - Roermund, van, A.H.M.

PY - 2006

Y1 - 2006

N2 - In this work, the design of an open-loop front-end track & hold (T&H) circuit is considered. Advantages of the presented circuit include low power-consumption, high-speed operation, simple reliable design, and ability to operate at low power-supplies. The major problem of open-loop circuits is their relatively poor linearity. In the presented design, high linearity is achieved by applying three linearization techniques: clock boosting (Abo and Gray, 1999), resistive source degeneration (Razavi, 2001), (Ouzounov et al., 2005) and cross-coupling (Ouzounov et al., 2005), (Voorman and Veenstra, 2000). As a result, a linearity corresponding to 10-bit accuracy is achieved. The final design in a 0.18mum CMOS process achieves an SFDR of 62 dB using a sample frequency of 500 MHz while consuming 15mW at a 1.8V power supply

AB - In this work, the design of an open-loop front-end track & hold (T&H) circuit is considered. Advantages of the presented circuit include low power-consumption, high-speed operation, simple reliable design, and ability to operate at low power-supplies. The major problem of open-loop circuits is their relatively poor linearity. In the presented design, high linearity is achieved by applying three linearization techniques: clock boosting (Abo and Gray, 1999), resistive source degeneration (Razavi, 2001), (Ouzounov et al., 2005) and cross-coupling (Ouzounov et al., 2005), (Voorman and Veenstra, 2000). As a result, a linearity corresponding to 10-bit accuracy is achieved. The final design in a 0.18mum CMOS process achieves an SFDR of 62 dB using a sample frequency of 500 MHz while consuming 15mW at a 1.8V power supply

U2 - 10.1109/NORCHP.2006.329254

DO - 10.1109/NORCHP.2006.329254

M3 - Conference contribution

SN - 1-4244-0772-9

SP - 103

EP - 106

BT - Proceedings of the 24th IEEE Norchip 2006 Conference

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - IEEE Norchip 2006

Y2 - 20 November 2006 through 21 November 2006

ER -

A 62dB SFDR, 500MSPS, 15mW open-loop track-and-hold circuit

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