A 6.1fJ/conv-step 0.0017mm2 Level Crossing ADC for Compressive Neural Sensing with Event-Driven Ramp Generation and Sparse DAC Switching Scheme

Stan van der Ven; Yuming He; Martijn Timmermans; Hua-Peng Liaw; Pieter Harpe; Roland van Wegberg; Eugenio Cantatore; Yao-Hong Liu

doi:10.1109/A-SSCC60305.2024.10848955

A 6.1fJ/conv-step 0.0017mm² Level Crossing ADC for Compressive Neural Sensing with Event-Driven Ramp Generation and Sparse DAC Switching Scheme

Stan van der Ven
, Yuming He
, Martijn Timmermans
, Hua-Peng Liaw
, Pieter Harpe
, Roland van Wegberg
, Eugenio Cantatore
, Yao-Hong Liu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

65 Downloads (Pure)

Abstract

This paper presents a dynamic level crossing ADC achieving a Walden FoM of 6.1fJ/conv-step and a data reduction of >10 × compared to conventional synchronous ADCs, while occupying an active area of only 0.0017mm². Asynchronous event generation within a low frequency clock period is exploited to significantly improve the energy efficiency without compromising in data reduction. To further improve energy efficiency, a novel DAC switching scheme optimized for sparse signals is presented. The presented LC-ADC supports 16 time-multiplexed neural sensing signals.

Original language	English
Title of host publication	2024 IEEE Asian Solid-State Circuits Conference, A-SSCC 2024
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	3
ISBN (Electronic)	979-8-3503-7632-6
DOIs	https://doi.org/10.1109/A-SSCC60305.2024.10848955
Publication status	Published - 28 Jan 2025
Event	2024 IEEE Asian Solid-State Circuits Conference, A-SSCC 2024 - Hiroshima, Japan Duration: 18 Nov 2024 → 21 Nov 2024

Conference

Conference	2024 IEEE Asian Solid-State Circuits Conference, A-SSCC 2024
Country/Territory	Japan
City	Hiroshima
Period	18/11/24 → 21/11/24

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Access to Document

10.1109/A-SSCC60305.2024.10848955

pdfFinal published version, 1.13 MBLicence: TAVERNE

Cite this

van der Ven, S., He, Y., Timmermans, M., Liaw, H.-P., Harpe, P., van Wegberg, R., Cantatore, E., & Liu, Y.-H. (2025). A 6.1fJ/conv-step 0.0017mm² Level Crossing ADC for Compressive Neural Sensing with Event-Driven Ramp Generation and Sparse DAC Switching Scheme. In 2024 IEEE Asian Solid-State Circuits Conference, A-SSCC 2024 Article 10848955 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/A-SSCC60305.2024.10848955

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title = "A 6.1fJ/conv-step 0.0017mm2 Level Crossing ADC for Compressive Neural Sensing with Event-Driven Ramp Generation and Sparse DAC Switching Scheme",

abstract = "This paper presents a dynamic level crossing ADC achieving a Walden FoM of 6.1fJ/conv-step and a data reduction of >10 {\texttimes} compared to conventional synchronous ADCs, while occupying an active area of only 0.0017mm2. Asynchronous event generation within a low frequency clock period is exploited to significantly improve the energy efficiency without compromising in data reduction. To further improve energy efficiency, a novel DAC switching scheme optimized for sparse signals is presented. The presented LC-ADC supports 16 time-multiplexed neural sensing signals.",

author = "\{van der Ven\}, Stan and Yuming He and Martijn Timmermans and Hua-Peng Liaw and Pieter Harpe and \{van Wegberg\}, Roland and Eugenio Cantatore and Yao-Hong Liu",

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van der Ven, S, He, Y, Timmermans, M, Liaw, H-P, Harpe, P, van Wegberg, R, Cantatore, E & Liu, Y-H 2025, A 6.1fJ/conv-step 0.0017mm² Level Crossing ADC for Compressive Neural Sensing with Event-Driven Ramp Generation and Sparse DAC Switching Scheme. in 2024 IEEE Asian Solid-State Circuits Conference, A-SSCC 2024., 10848955, Institute of Electrical and Electronics Engineers, 2024 IEEE Asian Solid-State Circuits Conference, A-SSCC 2024, Hiroshima, Japan, 18/11/24. https://doi.org/10.1109/A-SSCC60305.2024.10848955

A 6.1fJ/conv-step 0.0017mm² Level Crossing ADC for Compressive Neural Sensing with Event-Driven Ramp Generation and Sparse DAC Switching Scheme. / van der Ven, Stan; He, Yuming; Timmermans, Martijn et al.
2024 IEEE Asian Solid-State Circuits Conference, A-SSCC 2024. Institute of Electrical and Electronics Engineers, 2025. 10848955.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - This paper presents a dynamic level crossing ADC achieving a Walden FoM of 6.1fJ/conv-step and a data reduction of >10 × compared to conventional synchronous ADCs, while occupying an active area of only 0.0017mm2. Asynchronous event generation within a low frequency clock period is exploited to significantly improve the energy efficiency without compromising in data reduction. To further improve energy efficiency, a novel DAC switching scheme optimized for sparse signals is presented. The presented LC-ADC supports 16 time-multiplexed neural sensing signals.

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van der Ven S, He Y, Timmermans M, Liaw HP, Harpe P, van Wegberg R et al. A 6.1fJ/conv-step 0.0017mm² Level Crossing ADC for Compressive Neural Sensing with Event-Driven Ramp Generation and Sparse DAC Switching Scheme. In 2024 IEEE Asian Solid-State Circuits Conference, A-SSCC 2024. Institute of Electrical and Electronics Engineers. 2025. 10848955 doi: 10.1109/A-SSCC60305.2024.10848955