A 60 GHz phased array system evaluation based on a 5-bit phase shifter in CMOS technology

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Abstract

This paper explores a 60 GHz phased array system for ultra-high data rate communication in indoor environments. The channel modeling is addressed and the system link budget is calculated. A 16-element phased array system specifications are presented. This paper also presents the design of one of the key blocks - a 5-bit digitally controlled passive phase shifter. The switch-type phase shifter is implemented in 40 nm CMOS technology, with the maximum phase error of 4.68° and the rms gain error of 1.72 dB.
Original languageEnglish
Title of host publication23rd IEEE Symposium on Communications and Vehicular Technology in the Benelux (IEEE SCVT), 22 November 2016, Mons Belgium
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages1-4
Number of pages4
ISBN (Electronic)978-1-5090-4361-3
ISBN (Print)978-1-5090-4362-0
DOIs
Publication statusPublished - 22 Nov 2016
Event23rd IEEE Symposium on Communications and Vehicular Technology in the BeNeLux (IEEE SCVT 2016) - Mons, Belgium
Duration: 22 Nov 201622 Nov 2016
Conference number: 23

Conference

Conference23rd IEEE Symposium on Communications and Vehicular Technology in the BeNeLux (IEEE SCVT 2016)
Abbreviated titleSCVT 2016
CountryBelgium
CityMons
Period22/11/1622/11/16

Keywords

  • 60 GHz
  • phased array
  • CMOS
  • indoor environments
  • ultra-high data rate
  • phase shifter

Cite this

Wang, B., Gao, H., Ying, K., Matters-Kammerer, M. K., & Baltus, P. G. M. (2016). A 60 GHz phased array system evaluation based on a 5-bit phase shifter in CMOS technology. In 23rd IEEE Symposium on Communications and Vehicular Technology in the Benelux (IEEE SCVT), 22 November 2016, Mons Belgium (pp. 1-4). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/SCVT.2016.7797672, https://doi.org/10.1109/SCVT.2016.7797672
Wang, B. ; Gao, H. ; Ying, K. ; Matters-Kammerer, M.K. ; Baltus, P.G.M. / A 60 GHz phased array system evaluation based on a 5-bit phase shifter in CMOS technology. 23rd IEEE Symposium on Communications and Vehicular Technology in the Benelux (IEEE SCVT), 22 November 2016, Mons Belgium. Piscataway : Institute of Electrical and Electronics Engineers, 2016. pp. 1-4
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abstract = "This paper explores a 60 GHz phased array system for ultra-high data rate communication in indoor environments. The channel modeling is addressed and the system link budget is calculated. A 16-element phased array system specifications are presented. This paper also presents the design of one of the key blocks - a 5-bit digitally controlled passive phase shifter. The switch-type phase shifter is implemented in 40 nm CMOS technology, with the maximum phase error of 4.68° and the rms gain error of 1.72 dB.",
keywords = "60 GHz, phased array, CMOS, indoor environments, ultra-high data rate, phase shifter",
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Wang, B, Gao, H, Ying, K, Matters-Kammerer, MK & Baltus, PGM 2016, A 60 GHz phased array system evaluation based on a 5-bit phase shifter in CMOS technology. in 23rd IEEE Symposium on Communications and Vehicular Technology in the Benelux (IEEE SCVT), 22 November 2016, Mons Belgium. Institute of Electrical and Electronics Engineers, Piscataway, pp. 1-4, 23rd IEEE Symposium on Communications and Vehicular Technology in the BeNeLux (IEEE SCVT 2016), Mons, Belgium, 22/11/16. https://doi.org/10.1109/SCVT.2016.7797672, https://doi.org/10.1109/SCVT.2016.7797672

A 60 GHz phased array system evaluation based on a 5-bit phase shifter in CMOS technology. / Wang, B.; Gao, H.; Ying, K.; Matters-Kammerer, M.K.; Baltus, P.G.M.

23rd IEEE Symposium on Communications and Vehicular Technology in the Benelux (IEEE SCVT), 22 November 2016, Mons Belgium. Piscataway : Institute of Electrical and Electronics Engineers, 2016. p. 1-4.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AB - This paper explores a 60 GHz phased array system for ultra-high data rate communication in indoor environments. The channel modeling is addressed and the system link budget is calculated. A 16-element phased array system specifications are presented. This paper also presents the design of one of the key blocks - a 5-bit digitally controlled passive phase shifter. The switch-type phase shifter is implemented in 40 nm CMOS technology, with the maximum phase error of 4.68° and the rms gain error of 1.72 dB.

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Wang B, Gao H, Ying K, Matters-Kammerer MK, Baltus PGM. A 60 GHz phased array system evaluation based on a 5-bit phase shifter in CMOS technology. In 23rd IEEE Symposium on Communications and Vehicular Technology in the Benelux (IEEE SCVT), 22 November 2016, Mons Belgium. Piscataway: Institute of Electrical and Electronics Engineers. 2016. p. 1-4 https://doi.org/10.1109/SCVT.2016.7797672, https://doi.org/10.1109/SCVT.2016.7797672