A 60 GHz Down-conversion Passive Mixer in 65 nm CMOS Technology

Yang Liu, Yun Fang, Hao Gao

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

A passive down-conversion mixer in a 65nm buck CMOS process has been presented. The proposed mixer is consisted of a mixer-core and a folded OTA buffer. The mixer has a 3-dB bandwidth of 57~66 GHz, with a conversion gain of −2.7 ~ −5.4 dB. It requires a LO level of −5 dBm. The isolation between LO and RF ports is 10 dB. The total power consumption of the mixer is 1.4 mW, and the chip area is 0.4 mm 2 .
Original languageEnglish
Title of host publication2021 IEEE MTT-S International Wireless Symposium, IWS 2021 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers
Number of pages3
ISBN (Electronic)978-1-6654-3527-7
DOIs
Publication statusPublished - 10 Aug 2021
Event2021 IEEE MTT-S International Wireless Symposium, IWS 2021 - ZOOM Conference, Nanjing, China
Duration: 23 May 202126 May 2021

Conference

Conference2021 IEEE MTT-S International Wireless Symposium, IWS 2021
Country/TerritoryChina
CityNanjing
Period23/05/2126/05/21

Keywords

  • 60 GHz
  • CMOS
  • Passive mixer

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