A 60 GHz Digitally Controlled Phase Shifter in CMOS

Y. Yu, P.G.M. Baltus, A.H.M. Roermund, van, D. Jeurissen, A. Grauw, de, E. Heijden, van der, Ralf Pijper

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

47 Citations (Scopus)
452 Downloads (Pure)

Abstract

This paper presents a 60 GHz digitally controlled phase shifter in the 65 nm CMOS technology. Using a differential varactor-loaded transmission-line architecture, the phase shifter achieves a phase resolution of 22.5deg, an average insertion loss of 8.5 to 10.3 dB and a return loss of better than 10 dB from 55 to 65 GHz. The phase shifter occupies an area of only 0.2 mm2. To the knowledge of the authors, this is the first 60 GHz digitally controlled phase shifter with a phase resolution of 22.5deg in silicon reported to date. It is well suited for a 60 GHz phased array.
Original languageEnglish
Title of host publicationEuropean Solid State Circuits Conference, 34th (ESSCIRC2008), Proceedings Edinburgh, UK, September 15-19, 2008)
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages250-253
ISBN (Print)978-1-4244-2362-0
DOIs
Publication statusPublished - 2008

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