A 60 GHz Digitally Controlled Phase Shifter in CMOS

Y. Yu, P.G.M. Baltus, A.H.M. Roermund, van, D. Jeurissen, A. Grauw, de, E. Heijden, van der, Ralf Pijper

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

45 Citations (Scopus)
400 Downloads (Pure)

Abstract

This paper presents a 60 GHz digitally controlled phase shifter in the 65 nm CMOS technology. Using a differential varactor-loaded transmission-line architecture, the phase shifter achieves a phase resolution of 22.5deg, an average insertion loss of 8.5 to 10.3 dB and a return loss of better than 10 dB from 55 to 65 GHz. The phase shifter occupies an area of only 0.2 mm2. To the knowledge of the authors, this is the first 60 GHz digitally controlled phase shifter with a phase resolution of 22.5deg in silicon reported to date. It is well suited for a 60 GHz phased array.
Original languageEnglish
Title of host publicationEuropean Solid State Circuits Conference, 34th (ESSCIRC2008), Proceedings Edinburgh, UK, September 15-19, 2008)
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages250-253
ISBN (Print)978-1-4244-2362-0
DOIs
Publication statusPublished - 2008

Fingerprint

Phase shifters
Varactors
Insertion losses
Electric lines
Silicon

Cite this

Yu, Y., Baltus, P. G. M., Roermund, van, A. H. M., Jeurissen, D., Grauw, de, A., Heijden, van der, E., & Pijper, R. (2008). A 60 GHz Digitally Controlled Phase Shifter in CMOS. In European Solid State Circuits Conference, 34th (ESSCIRC2008), Proceedings Edinburgh, UK, September 15-19, 2008) (pp. 250-253). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIRC.2008.4681839
Yu, Y. ; Baltus, P.G.M. ; Roermund, van, A.H.M. ; Jeurissen, D. ; Grauw, de, A. ; Heijden, van der, E. ; Pijper, Ralf. / A 60 GHz Digitally Controlled Phase Shifter in CMOS. European Solid State Circuits Conference, 34th (ESSCIRC2008), Proceedings Edinburgh, UK, September 15-19, 2008). Piscataway : Institute of Electrical and Electronics Engineers, 2008. pp. 250-253
@inproceedings{8b4cc62d04bc4f9981ef8f7662a1e1ed,
title = "A 60 GHz Digitally Controlled Phase Shifter in CMOS",
abstract = "This paper presents a 60 GHz digitally controlled phase shifter in the 65 nm CMOS technology. Using a differential varactor-loaded transmission-line architecture, the phase shifter achieves a phase resolution of 22.5deg, an average insertion loss of 8.5 to 10.3 dB and a return loss of better than 10 dB from 55 to 65 GHz. The phase shifter occupies an area of only 0.2 mm2. To the knowledge of the authors, this is the first 60 GHz digitally controlled phase shifter with a phase resolution of 22.5deg in silicon reported to date. It is well suited for a 60 GHz phased array.",
author = "Y. Yu and P.G.M. Baltus and {Roermund, van}, A.H.M. and D. Jeurissen and {Grauw, de}, A. and {Heijden, van der}, E. and Ralf Pijper",
year = "2008",
doi = "10.1109/ESSCIRC.2008.4681839",
language = "English",
isbn = "978-1-4244-2362-0",
pages = "250--253",
booktitle = "European Solid State Circuits Conference, 34th (ESSCIRC2008), Proceedings Edinburgh, UK, September 15-19, 2008)",
publisher = "Institute of Electrical and Electronics Engineers",
address = "United States",

}

Yu, Y, Baltus, PGM, Roermund, van, AHM, Jeurissen, D, Grauw, de, A, Heijden, van der, E & Pijper, R 2008, A 60 GHz Digitally Controlled Phase Shifter in CMOS. in European Solid State Circuits Conference, 34th (ESSCIRC2008), Proceedings Edinburgh, UK, September 15-19, 2008). Institute of Electrical and Electronics Engineers, Piscataway, pp. 250-253. https://doi.org/10.1109/ESSCIRC.2008.4681839

A 60 GHz Digitally Controlled Phase Shifter in CMOS. / Yu, Y.; Baltus, P.G.M.; Roermund, van, A.H.M.; Jeurissen, D.; Grauw, de, A.; Heijden, van der, E.; Pijper, Ralf.

European Solid State Circuits Conference, 34th (ESSCIRC2008), Proceedings Edinburgh, UK, September 15-19, 2008). Piscataway : Institute of Electrical and Electronics Engineers, 2008. p. 250-253.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - A 60 GHz Digitally Controlled Phase Shifter in CMOS

AU - Yu, Y.

AU - Baltus, P.G.M.

AU - Roermund, van, A.H.M.

AU - Jeurissen, D.

AU - Grauw, de, A.

AU - Heijden, van der, E.

AU - Pijper, Ralf

PY - 2008

Y1 - 2008

N2 - This paper presents a 60 GHz digitally controlled phase shifter in the 65 nm CMOS technology. Using a differential varactor-loaded transmission-line architecture, the phase shifter achieves a phase resolution of 22.5deg, an average insertion loss of 8.5 to 10.3 dB and a return loss of better than 10 dB from 55 to 65 GHz. The phase shifter occupies an area of only 0.2 mm2. To the knowledge of the authors, this is the first 60 GHz digitally controlled phase shifter with a phase resolution of 22.5deg in silicon reported to date. It is well suited for a 60 GHz phased array.

AB - This paper presents a 60 GHz digitally controlled phase shifter in the 65 nm CMOS technology. Using a differential varactor-loaded transmission-line architecture, the phase shifter achieves a phase resolution of 22.5deg, an average insertion loss of 8.5 to 10.3 dB and a return loss of better than 10 dB from 55 to 65 GHz. The phase shifter occupies an area of only 0.2 mm2. To the knowledge of the authors, this is the first 60 GHz digitally controlled phase shifter with a phase resolution of 22.5deg in silicon reported to date. It is well suited for a 60 GHz phased array.

U2 - 10.1109/ESSCIRC.2008.4681839

DO - 10.1109/ESSCIRC.2008.4681839

M3 - Conference contribution

SN - 978-1-4244-2362-0

SP - 250

EP - 253

BT - European Solid State Circuits Conference, 34th (ESSCIRC2008), Proceedings Edinburgh, UK, September 15-19, 2008)

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Yu Y, Baltus PGM, Roermund, van AHM, Jeurissen D, Grauw, de A, Heijden, van der E et al. A 60 GHz Digitally Controlled Phase Shifter in CMOS. In European Solid State Circuits Conference, 34th (ESSCIRC2008), Proceedings Edinburgh, UK, September 15-19, 2008). Piscataway: Institute of Electrical and Electronics Engineers. 2008. p. 250-253 https://doi.org/10.1109/ESSCIRC.2008.4681839