A 60 GHz 5-bit digital controlled phase shifter in a digital 40-nm CMOS technology without ultra-thick metals

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Abstract

A 5-bit digital controlled switch-type passive phase shifter realised in a 40 nm digital CMOS technology without ultra-thick metals for the 60 GHz Industrial, Scientific and Medical (ISM) band is presented. A patterned shielding with electromagnetic bandgap structure and a stacked metals method to increase the on-chip inductor quality factor are proposed. To reduce the insertion loss from the transistors, the transistor switches are implemented with a body-source connection. For all 32 states, the minimum phase error is 1.5°, and the maximum phase error is 6.8°. The measured insertion loss is -20.9 ± 1 dB including pad loss at 60 GHz and the return loss is >10 dB over 57-64 GHz. The total chip size is 0.24 mm2 with 0 mW DC power consumption.
Original languageEnglish
Pages (from-to)1611-1613
Number of pages3
JournalElectronics Letters
Volume52
Issue number19
DOIs
Publication statusPublished - 15 Sep 2016

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Phase shifters
Insertion losses
Transistors
Switches
Metals
Shielding
Energy gap
Electric power utilization

Cite this

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title = "A 60 GHz 5-bit digital controlled phase shifter in a digital 40-nm CMOS technology without ultra-thick metals",
abstract = "A 5-bit digital controlled switch-type passive phase shifter realised in a 40 nm digital CMOS technology without ultra-thick metals for the 60 GHz Industrial, Scientific and Medical (ISM) band is presented. A patterned shielding with electromagnetic bandgap structure and a stacked metals method to increase the on-chip inductor quality factor are proposed. To reduce the insertion loss from the transistors, the transistor switches are implemented with a body-source connection. For all 32 states, the minimum phase error is 1.5°, and the maximum phase error is 6.8°. The measured insertion loss is -20.9 ± 1 dB including pad loss at 60 GHz and the return loss is >10 dB over 57-64 GHz. The total chip size is 0.24 mm2 with 0 mW DC power consumption.",
author = "H. Gao and K. Ying and {Matters - Kammerer}, M. and P. Harpe and B. Wang and B. Liu and W. Serdijn and P. Baltus",
year = "2016",
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language = "English",
volume = "52",
pages = "1611--1613",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology (IET)",
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A 60 GHz 5-bit digital controlled phase shifter in a digital 40-nm CMOS technology without ultra-thick metals. / Gao, H.; Ying, K.; Matters - Kammerer, M.; Harpe, P.; Wang, B.; Liu, B.; Serdijn, W.; Baltus, P.

In: Electronics Letters, Vol. 52, No. 19, 15.09.2016, p. 1611-1613.

Research output: Contribution to journalArticleAcademicpeer-review

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T1 - A 60 GHz 5-bit digital controlled phase shifter in a digital 40-nm CMOS technology without ultra-thick metals

AU - Gao, H.

AU - Ying, K.

AU - Matters - Kammerer, M.

AU - Harpe, P.

AU - Wang, B.

AU - Liu, B.

AU - Serdijn, W.

AU - Baltus, P.

PY - 2016/9/15

Y1 - 2016/9/15

N2 - A 5-bit digital controlled switch-type passive phase shifter realised in a 40 nm digital CMOS technology without ultra-thick metals for the 60 GHz Industrial, Scientific and Medical (ISM) band is presented. A patterned shielding with electromagnetic bandgap structure and a stacked metals method to increase the on-chip inductor quality factor are proposed. To reduce the insertion loss from the transistors, the transistor switches are implemented with a body-source connection. For all 32 states, the minimum phase error is 1.5°, and the maximum phase error is 6.8°. The measured insertion loss is -20.9 ± 1 dB including pad loss at 60 GHz and the return loss is >10 dB over 57-64 GHz. The total chip size is 0.24 mm2 with 0 mW DC power consumption.

AB - A 5-bit digital controlled switch-type passive phase shifter realised in a 40 nm digital CMOS technology without ultra-thick metals for the 60 GHz Industrial, Scientific and Medical (ISM) band is presented. A patterned shielding with electromagnetic bandgap structure and a stacked metals method to increase the on-chip inductor quality factor are proposed. To reduce the insertion loss from the transistors, the transistor switches are implemented with a body-source connection. For all 32 states, the minimum phase error is 1.5°, and the maximum phase error is 6.8°. The measured insertion loss is -20.9 ± 1 dB including pad loss at 60 GHz and the return loss is >10 dB over 57-64 GHz. The total chip size is 0.24 mm2 with 0 mW DC power consumption.

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