A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS

Qilong Liu, Lucien Breems, Chenming Zhang, Shagun Bajoria, Muhammed Bolatkale, Robert Rutten, Georgi Radulov

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

9 Citations (Scopus)
10 Downloads (Pure)


In the pursuit of ever larger bandwidths, in recent years GHz-rate continuous-time (CT) oversampled ADCs have been reported in literature that achieve bandwidths of hundreds of MHz and have even exceeded the GHz barrier [1]-[3]. As impressive as these bandwidths are for CT ADCs, the required ADC architectures are complex, are sensitive to layout parasitics due to the high sampling rates, and most important of all, are power hungry, consuming several hundreds of mW. In this paper, we propose a filtering rnulti-stage noise-shaping (MASH) ΔΣ ADC architecture that overcomes the abovementioned drawbacks. Passive delay compensating filters [4] are used to realize broadband and deep suppression of the input signal component at the internal filter nodes of the ADC. As a result, no interstage DACs are needed, which are commonly required to generate the quantization error replicas in a MASH ΔΣ ADC, saving substantial power and greatly reducing the parasitic load of the high-speed critical nodes. Moreover, because of the absence of signal content at the internal filter nodes, the backend stages of the MASH architecture have relaxed linearity requirements and can be implemented with simple low-power Gm-C filters. Precise excess loop delay and excess phase compensation are accomplished with a partly resistive and capacitive stabilization DAC, enabling very-high-speed operation of the ΔΣ loops. The realized MASH ADC is sampled at 5GHz and achieves 68dB/65dB DR/peak SNDR over a 360MHz bandwidth, -78dBc THD at -1dBFS for a 115MHz input signal, and consumes 158mW. Implemented in a mature 40nm CMOS technology, the ADC occupies only 0.21 mm2 core area, achieves 2× lower power, 5dB higher Schreier FOM and 2× lower Walden FOM compared to state-of-the-art broadband CT ADCs in advanced 16nm-28nm nodes [1]-[3].

Original languageEnglish
Title of host publication2022 IEEE International Solid-State Circuits Conference (ISSCC 2022)
PublisherInstitute of Electrical and Electronics Engineers
Number of pages3
ISBN (Electronic)978-1-6654-2800-2
Publication statusPublished - 17 Mar 2022
Event2022 IEEE International Solid-State Circuits Conference, ISSCC 2022 - San Francisco, United States
Duration: 20 Feb 202226 Feb 2022


Conference2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
Country/TerritoryUnited States
CitySan Francisco


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