A 5bit 1GS/s 2.7mW 0.05mm^2 asynchronous digital slope ADC in 90nm CMOS for IR UWB radio

M. Ding, P.J.A. Harpe, J.A. Hegt, K.J.P. Philips, H.W.H. Groot, de, A.H.M. Roermund, van

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

4 Citations (Scopus)

Abstract

A 5bit 1GS/s 0.05mm2 4× time-interleaved asynchronous digital slope ADC in 90nm CMOS for IR UWB radio is presented. New delay cells are introduced to double the speed over prior art, yielding the 250MS/s single-channel slope converter. A self-disabled comparator eliminates static leakage and consumes only 0.25pJ/conversion. A single calibration circuit corrects both offset errors and mismatches in the new delay cells, achieving an ENOB of 4.85bit with 1.5GHz ERBW. This ADC consumes 2.7mW at a 1V supply, enabling a FoM of 93fJ/conversion-step. At 0.8V, it can work at 0.5GS/s. Even compared to the state-of-the-art of well-established architectures, it achieves similar power-efficiency.
Original languageEnglish
Title of host publicationProceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 17 - 19 June 2012, Montreal, Canada
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages487-490
DOIs
Publication statusPublished - 2012
Event2012 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2012) - Montréal, Canada
Duration: 17 Jun 201219 Jun 2012

Conference

Conference2012 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2012)
Abbreviated titleRFIC 2012
CountryCanada
CityMontréal
Period17/06/1219/06/12

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Ding, M., Harpe, P. J. A., Hegt, J. A., Philips, K. J. P., Groot, de, H. W. H., & Roermund, van, A. H. M. (2012). A 5bit 1GS/s 2.7mW 0.05mm^2 asynchronous digital slope ADC in 90nm CMOS for IR UWB radio. In Proceedings of the Radio Frequency Integrated Circuits Symposium (RFIC), 17 - 19 June 2012, Montreal, Canada (pp. 487-490). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/RFIC.2012.6242328