Abstract
A common choice for digitizing biomedical signals is the SAR ADC, which is often preferred due to its high power efficiency. A different architecture which, like the SAR ADC, only consists of a DAC, a comparator and digital logic, is a level crossing (LC) ADC. The main difference is that an LC ADC quantizes amplitude instead of time. This architecture has potential advantages over the SAR ADC. Firstly, the output spectrum is alias free, which is due to its non-uniform sampling. Secondly, the output is event driven. This can lead to data reduction and lower power when digitizing sparse signals. Lastly, the SNDR of the reconstructed signal is independent of the resolution of the DAC, as long as the average sampling rate meets the Nyquist rate of the input signal. By decoupling the SNDR from the amplitude resolution, it is possible to use a small DAC even when high SNDR is desired. This is not the case for SAR ADCs, where the DAC usually dominates the area for high SNDR applications. Hence, it should be expected that an LC ADC can be smaller than SAR ADCs. So far, to the best of the author’s knowledge, no prior work reported this. The aim of this work is to offer architectural improvements to design a small area LC ADC, while not compromising on SNDR. The paper covers also an additional architectural improvement, to lower the standby power consumption.
Original language | English |
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Publication status | Published - 8 Jul 2021 |
Event | 2021 ProRISC Conference on Integrated circuit design (ProRISC 2021) - University of Technology Eindhoven, Eindhoven, Netherlands Duration: 8 Jul 2021 → 9 Jul 2021 https://prorisc-safe.nl/ |
Conference
Conference | 2021 ProRISC Conference on Integrated circuit design (ProRISC 2021) |
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Abbreviated title | ProRISC 2021 |
Country/Territory | Netherlands |
City | Eindhoven |
Period | 8/07/21 → 9/07/21 |
Internet address |