A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter

Fred Mostert, Daniel Schinkel, Wouter Groothedde, Lucien Breems, Remko van Heeswijk, Marto Jan Koerts, Eric Van Iersel, Daniel Groeneveld, Gertjan van Holland, Patrick Zeelen, Derk Jan Hissink, Martin Pos, Paul Wielage, Fre Jorritsma, Marc Klein Middelink

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

8 Citations (Scopus)
2 Downloads (Pure)

Abstract

Feedback after the output filter has long been a desired feature for high-power switching (Class-D) amplifiers, as it mitigates the influence of the LC filter components on the frequency transfer function and on linearity, enabling lower component costs. However, it requires compensation of the LC filter to maintain loop stability. In the analog domain, this is difficult to combine with high loop-gain, as the design has to cope with variability in both the LC filter and in the loop-filter. In [1], multiple analog feedback loop-filters from before and after the output filter have been employed, but the loop-gain of the outer loop is only ∼10dB at 20kHz. Alternatively, digital filters have no variability in their coefficients and are well suited for programmable compensation of the output filter, optionally even adaptive. In [2] feasibility is shown of a single digital loop with full global feedback. However, to achieve this, a costly commercially available ADC with 2.5MHz bandwidth and 950mW power consumption was required, a drawback that so far has prevented further adoption. In this paper we present a 5-channel Class-D amplifier with integrated low-latency delta-sigma (ΔΣ) ADCs, each consuming only 30mW, for digital feedback after the output filter. With this system, more than 50dB loop-gain is obtained. THD+N is 0.004% over the full audio band, which is at least 10× better than [1] where data is only given at 1kHz.

Original languageEnglish
Title of host publication2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages86-87
Number of pages2
ISBN (Electronic)9781509037575
DOIs
Publication statusPublished - 2 Mar 2017
Event64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States
Duration: 5 Feb 20179 Feb 2017
Conference number: 64

Conference

Conference64th IEEE International Solid-State Circuits Conference, ISSCC 2017
Abbreviated titleISSCC 2017
Country/TerritoryUnited States
CitySan Francisco
Period5/02/179/02/17

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