This paper presents the design and implementation of a variable gain amplifier with an ultra low-power consumption of 56µW. This is achieved by using sub-threshold operation, 1V power supply and a minimum amount of current branches. After system-level optimization, a gain range of 47dB is implemented with 6dB per step programmability. The SNDR is better than 33dB for all gain settings, while the nominal signal bandwidth is 5MHz. The performance is measured on a test-chip in a 90nm CMOS technology.
|Title of host publication||Proceedings of the 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 26-30 April 2010, Hsinchu, Taiwan|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2010|