A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme

M. Ding, P.J.A. Harpe, Y.-H. Liu, B. Büsze, K.J.P. Philips, H.W.H. Groot, de

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

29 Citations (Scopus)
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Abstract

Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.
Original languageEnglish
Title of host publicationProceedings of the IEEE International Solid-State Circuits Conference, 22-26 Februari 2015, San Francisco, California
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages460-461
ISBN (Print)978-1-4799-6223-5
DOIs
Publication statusPublished - 2015
Event62nd IEEE International Solid-State Circuits Conference,(ISSCC 2015) - San Francisco Marriott, San Francisco, United States
Duration: 22 Feb 201526 Feb 2015
Conference number: 62

Conference

Conference62nd IEEE International Solid-State Circuits Conference,(ISSCC 2015)
Abbreviated titleISSCC 2015
CountryUnited States
CitySan Francisco
Period22/02/1526/02/15

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Error detection
Redundancy
Calibration
Capacitors
Sampling
Networks (circuits)

Cite this

Ding, M., Harpe, P. J. A., Liu, Y-H., Büsze, B., Philips, K. J. P., & Groot, de, H. W. H. (2015). A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme. In Proceedings of the IEEE International Solid-State Circuits Conference, 22-26 Februari 2015, San Francisco, California (pp. 460-461). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSCC.2015.7063125
Ding, M. ; Harpe, P.J.A. ; Liu, Y.-H. ; Büsze, B. ; Philips, K.J.P. ; Groot, de, H.W.H. / A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme. Proceedings of the IEEE International Solid-State Circuits Conference, 22-26 Februari 2015, San Francisco, California. Piscataway : Institute of Electrical and Electronics Engineers, 2015. pp. 460-461
@inproceedings{e80b65759e3c40b6a95ec7196235267b,
title = "A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme",
abstract = "Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.",
author = "M. Ding and P.J.A. Harpe and Y.-H. Liu and B. B{\"u}sze and K.J.P. Philips and {Groot, de}, H.W.H.",
year = "2015",
doi = "10.1109/ISSCC.2015.7063125",
language = "English",
isbn = "978-1-4799-6223-5",
pages = "460--461",
booktitle = "Proceedings of the IEEE International Solid-State Circuits Conference, 22-26 Februari 2015, San Francisco, California",
publisher = "Institute of Electrical and Electronics Engineers",
address = "United States",

}

Ding, M, Harpe, PJA, Liu, Y-H, Büsze, B, Philips, KJP & Groot, de, HWH 2015, A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme. in Proceedings of the IEEE International Solid-State Circuits Conference, 22-26 Februari 2015, San Francisco, California. Institute of Electrical and Electronics Engineers, Piscataway, pp. 460-461, 62nd IEEE International Solid-State Circuits Conference,(ISSCC 2015), San Francisco, United States, 22/02/15. https://doi.org/10.1109/ISSCC.2015.7063125

A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme. / Ding, M.; Harpe, P.J.A.; Liu, Y.-H.; Büsze, B.; Philips, K.J.P.; Groot, de, H.W.H.

Proceedings of the IEEE International Solid-State Circuits Conference, 22-26 Februari 2015, San Francisco, California. Piscataway : Institute of Electrical and Electronics Engineers, 2015. p. 460-461.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme

AU - Ding, M.

AU - Harpe, P.J.A.

AU - Liu, Y.-H.

AU - Büsze, B.

AU - Philips, K.J.P.

AU - Groot, de, H.W.H.

PY - 2015

Y1 - 2015

N2 - Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.

AB - Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.

U2 - 10.1109/ISSCC.2015.7063125

DO - 10.1109/ISSCC.2015.7063125

M3 - Conference contribution

SN - 978-1-4799-6223-5

SP - 460

EP - 461

BT - Proceedings of the IEEE International Solid-State Circuits Conference, 22-26 Februari 2015, San Francisco, California

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Ding M, Harpe PJA, Liu Y-H, Büsze B, Philips KJP, Groot, de HWH. A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme. In Proceedings of the IEEE International Solid-State Circuits Conference, 22-26 Februari 2015, San Francisco, California. Piscataway: Institute of Electrical and Electronics Engineers. 2015. p. 460-461 https://doi.org/10.1109/ISSCC.2015.7063125