Abstract
Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.
Original language | English |
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Title of host publication | Proceedings of the IEEE International Solid-State Circuits Conference, 22-26 Februari 2015, San Francisco, California |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 460-461 |
ISBN (Print) | 978-1-4799-6223-5 |
DOIs | |
Publication status | Published - 2015 |
Event | 62nd IEEE International Solid-State Circuits Conference,(ISSCC 2015) - San Francisco Marriott, San Francisco, United States Duration: 22 Feb 2015 → 26 Feb 2015 Conference number: 62 |
Conference
Conference | 62nd IEEE International Solid-State Circuits Conference,(ISSCC 2015) |
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Abbreviated title | ISSCC 2015 |
Country | United States |
City | San Francisco |
Period | 22/02/15 → 26/02/15 |