A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method

H. Gao; K. Ying; M.K. Matters-Kammerer; P. Harpe; Q. Ma; A. van Roermund; P. Baltus

doi:10.1109/RFIC.2016.7508274

A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method

H. Gao, K. Ying, M.K. Matters-Kammerer, P. Harpe, Q. Ma, A. van Roermund, P. Baltus

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

51 Citations (Scopus)

21 Downloads (Pure)

Abstract

This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.

Original language	English
Title of host publication	2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Editors	S. Mehta, L. Lin
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	154-157
Number of pages	4
ISBN (Electronic)	978-1-4673-8651-7
ISBN (Print)	978-1-4673-8650-0
DOIs	https://doi.org/10.1109/RFIC.2016.7508274
Publication status	Published - 22 May 2016
Event	2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2016) - Moscone Convention Center, San Francisco, United States Duration: 22 May 2016 → 24 May 2016

Conference

Conference	2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2016)
Abbreviated title	RFIC 2016
Country/Territory	United States
City	San Francisco
Period	22/05/16 → 24/05/16

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10.1109/RFIC.2016.7508274

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Gao, H., Ying, K., Matters-Kammerer, M. K., Harpe, P., Ma, Q., van Roermund, A., & Baltus, P. (2016). A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method. In S. Mehta, & L. Lin (Eds.), 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (pp. 154-157). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/RFIC.2016.7508274

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title = "A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method",

abstract = "This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.",

author = "H. Gao and K. Ying and M.K. Matters-Kammerer and P. Harpe and Q. Ma and {van Roermund}, A. and P. Baltus",

year = "2016",

month = may,

day = "22",

doi = "10.1109/RFIC.2016.7508274",

language = "English",

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pages = "154--157",

editor = "S. Mehta and Lin, {L. }",

booktitle = "2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2016), RFIC 2016 ; Conference date: 22-05-2016 Through 24-05-2016",

}

Gao, H, Ying, K, Matters-Kammerer, MK , Harpe, P, Ma, Q, van Roermund, A & Baltus, P 2016, A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method. in S Mehta & L Lin (eds), 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). Institute of Electrical and Electronics Engineers, Piscataway, pp. 154-157, 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2016), San Francisco, California, United States, 22/05/16. https://doi.org/10.1109/RFIC.2016.7508274

A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method. / Gao, H.; Ying, K.; Matters-Kammerer, M.K. et al.
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). ed. / S. Mehta; L. Lin. Piscataway: Institute of Electrical and Electronics Engineers, 2016. p. 154-157.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Gao, H.

AU - Ying, K.

AU - Matters-Kammerer, M.K.

AU - Harpe, P.

AU - Ma, Q.

AU - van Roermund, A.

AU - Baltus, P.

PY - 2016/5/22

Y1 - 2016/5/22

N2 - This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.

AB - This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.

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DO - 10.1109/RFIC.2016.7508274

M3 - Conference contribution

SN - 978-1-4673-8650-0

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EP - 157

BT - 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

A2 - Mehta, S.

A2 - Lin, L.

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2016)

Y2 - 22 May 2016 through 24 May 2016

ER -

A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method

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