A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method

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Abstract

This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.
Original languageEnglish
Title of host publication2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
EditorsS. Mehta, L. Lin
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages154-157
Number of pages4
ISBN (Electronic)978-1-4673-8651-7
ISBN (Print) 978-1-4673-8650-0
DOIs
Publication statusPublished - 22 May 2016
Event2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2016) - Moscone Convention Center, San Francisco, United States
Duration: 22 May 201624 May 2016

Conference

Conference2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2016)
Abbreviated titleRFIC 2016
CountryUnited States
CitySan Francisco
Period22/05/1624/05/16

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Gao, H., Ying, K., Matters-Kammerer, M. K., Harpe, P., Ma, Q., van Roermund, A., & Baltus, P. (2016). A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method. In S. Mehta, & L. Lin (Eds.), 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (pp. 154-157). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/RFIC.2016.7508274