A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist

K. Doris; E. Janssen; C. Nani; A. Zanikopoulos; G. Weide, van der

doi:10.1109/ISSCC.2011.5746272

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist

K. Doris, E. Janssen, C. Nani, A. Zanikopoulos, G. Weide, van der

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

57 Citations (Scopus)

Abstract

Trends in cable TV reception for data and video require simultaneous capture of many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die could be simplified with a low-power 10b ADC that can digitize the entire TV band and be suitable for integration with baseband DSP. This work presents a 64¿ inter leaved 2.6GS/S 10b 65nm CMOS ADC with on-chip calibrations, combining interleaving hierarchy with an open-loop buffer array operated in feedforward sampling and feedback-SAR mode. The ADC achieves an SNDR of 48.5dB at Nyquist and consumes only 0.48W.

Original language	English
Title of host publication	Proceeding of the Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 20-24 February 2011, San Francisco
Editors	L.C. Fujino
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	180-182
ISBN (Print)	978-1-61284-302-5
DOIs	https://doi.org/10.1109/ISSCC.2011.5746272
Publication status	Published - 2011
Event	58th IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, United States Duration: 20 Feb 2011 → 24 Feb 2011 Conference number: 58

Conference

Conference	58th IEEE International Solid-State Circuits Conference, ISSCC 2011
Abbreviated title	ISSCC 2011
Country/Territory	United States
City	San Francisco
Period	20/02/11 → 24/02/11
Other	“Electronics for Healthy Living”

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10.1109/ISSCC.2011.5746272

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Doris, K., Janssen, E., Nani, C., Zanikopoulos, A., & Weide, van der, G. (2011). A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist. In L. C. Fujino (Ed.), Proceeding of the Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 20-24 February 2011, San Francisco (pp. 180-182). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSCC.2011.5746272

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abstract = "Trends in cable TV reception for data and video require simultaneous capture of many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die could be simplified with a low-power 10b ADC that can digitize the entire TV band and be suitable for integration with baseband DSP. This work presents a 64¿ inter leaved 2.6GS/S 10b 65nm CMOS ADC with on-chip calibrations, combining interleaving hierarchy with an open-loop buffer array operated in feedforward sampling and feedback-SAR mode. The ADC achieves an SNDR of 48.5dB at Nyquist and consumes only 0.48W.",

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Doris, K, Janssen, E, Nani, C, Zanikopoulos, A & Weide, van der, G 2011, A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist. in LC Fujino (ed.), Proceeding of the Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 20-24 February 2011, San Francisco. Institute of Electrical and Electronics Engineers, Piscataway, pp. 180-182, 58th IEEE International Solid-State Circuits Conference, ISSCC 2011, San Francisco, California, United States, 20/02/11. https://doi.org/10.1109/ISSCC.2011.5746272

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist. / Doris, K.; Janssen, E.; Nani, C. et al.
Proceeding of the Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 20-24 February 2011, San Francisco. ed. / L.C. Fujino. Piscataway: Institute of Electrical and Electronics Engineers, 2011. p. 180-182.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Doris K, Janssen E, Nani C, Zanikopoulos A, Weide, van der G. A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist. In Fujino LC, editor, Proceeding of the Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 20-24 February 2011, San Francisco. Piscataway: Institute of Electrical and Electronics Engineers. 2011. p. 180-182 doi: 10.1109/ISSCC.2011.5746272

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist

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