A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area

Y. Xu; P. Harpe; T. Ytterdal

doi:10.1109/ISCAS.2015.7169177

A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area

Y. Xu, P. Harpe, T. Ytterdal

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

Abstract

Good energy efficiency and area efficiency are both achieved for the presented 9-bit 35MS/s SAR ADC, by using customized small-value capacitors in a splitting monotonic switching scheme, a simplified dynamic digital logic and a self-clocked dynamic comparator. With built-in configurable gain, the ADC maintains its peak SNDR over a wide input range, featuring more flexibility. Fabricated in a 65nm CMOS technology, the ADC consumes 46.1μW at 35MS/s from 1V supply voltage, and achieves an SNDR of 51dB and an ENOB of 8.18bits at Nyquist rate, resulting in a figure of merit (FoM) of 4.5fJ/conversion-step. The core circuit only occupies 0.009mm², which is very compact.

Original language	English
Title of host publication	2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal, 24 - 27 May 2015
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	2437-2440
Number of pages	4
ISBN (Print)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7169177
Publication status	Published - 27 Jul 2015
Event	2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015) - Lisbon, Portugal, Lisbon, Portugal Duration: 24 May 2015 → 27 May 2015 http://www.iscas2015.org/

Conference

Conference	2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015)
Abbreviated title	ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	24/05/15 → 27/05/15
Internet address	http://www.iscas2015.org/

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10.1109/ISCAS.2015.7169177

Cite this

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title = "A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area",

abstract = "Good energy efficiency and area efficiency are both achieved for the presented 9-bit 35MS/s SAR ADC, by using customized small-value capacitors in a splitting monotonic switching scheme, a simplified dynamic digital logic and a self-clocked dynamic comparator. With built-in configurable gain, the ADC maintains its peak SNDR over a wide input range, featuring more flexibility. Fabricated in a 65nm CMOS technology, the ADC consumes 46.1μW at 35MS/s from 1V supply voltage, and achieves an SNDR of 51dB and an ENOB of 8.18bits at Nyquist rate, resulting in a figure of merit (FoM) of 4.5fJ/conversion-step. The core circuit only occupies 0.009mm2, which is very compact.",

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publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), ISCAS 2015 ; Conference date: 24-05-2015 Through 27-05-2015",

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Xu, Y, Harpe, P & Ytterdal, T 2015, A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area. in 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal, 24 - 27 May 2015., 7169177, Institute of Electrical and Electronics Engineers, Piscataway, pp. 2437-2440, 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal, 24/05/15. https://doi.org/10.1109/ISCAS.2015.7169177

A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area. / Xu, Y.; Harpe, P.; Ytterdal, T.

2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal, 24 - 27 May 2015. Piscataway : Institute of Electrical and Electronics Engineers, 2015. p. 2437-2440 7169177.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Harpe, P.

AU - Ytterdal, T.

PY - 2015/7/27

Y1 - 2015/7/27

N2 - Good energy efficiency and area efficiency are both achieved for the presented 9-bit 35MS/s SAR ADC, by using customized small-value capacitors in a splitting monotonic switching scheme, a simplified dynamic digital logic and a self-clocked dynamic comparator. With built-in configurable gain, the ADC maintains its peak SNDR over a wide input range, featuring more flexibility. Fabricated in a 65nm CMOS technology, the ADC consumes 46.1μW at 35MS/s from 1V supply voltage, and achieves an SNDR of 51dB and an ENOB of 8.18bits at Nyquist rate, resulting in a figure of merit (FoM) of 4.5fJ/conversion-step. The core circuit only occupies 0.009mm2, which is very compact.

AB - Good energy efficiency and area efficiency are both achieved for the presented 9-bit 35MS/s SAR ADC, by using customized small-value capacitors in a splitting monotonic switching scheme, a simplified dynamic digital logic and a self-clocked dynamic comparator. With built-in configurable gain, the ADC maintains its peak SNDR over a wide input range, featuring more flexibility. Fabricated in a 65nm CMOS technology, the ADC consumes 46.1μW at 35MS/s from 1V supply voltage, and achieves an SNDR of 51dB and an ENOB of 8.18bits at Nyquist rate, resulting in a figure of merit (FoM) of 4.5fJ/conversion-step. The core circuit only occupies 0.009mm2, which is very compact.

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ER -

A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area

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