A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area

Y. Xu, P. Harpe, T. Ytterdal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)

Abstract

Good energy efficiency and area efficiency are both achieved for the presented 9-bit 35MS/s SAR ADC, by using customized small-value capacitors in a splitting monotonic switching scheme, a simplified dynamic digital logic and a self-clocked dynamic comparator. With built-in configurable gain, the ADC maintains its peak SNDR over a wide input range, featuring more flexibility. Fabricated in a 65nm CMOS technology, the ADC consumes 46.1μW at 35MS/s from 1V supply voltage, and achieves an SNDR of 51dB and an ENOB of 8.18bits at Nyquist rate, resulting in a figure of merit (FoM) of 4.5fJ/conversion-step. The core circuit only occupies 0.009mm2, which is very compact.

Original languageEnglish
Title of host publication2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal, 24 - 27 May 2015
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages2437-2440
Number of pages4
ISBN (Print)9781479983919
DOIs
Publication statusPublished - 27 Jul 2015
Event2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015) - Lisbon, Portugal
Duration: 24 May 201527 May 2015
http://www.iscas2015.org/

Conference

Conference2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015)
Abbreviated titleISCAS 2015
CountryPortugal
CityLisbon
Period24/05/1527/05/15
Internet address

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Cite this

Xu, Y., Harpe, P., & Ytterdal, T. (2015). A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area. In 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal, 24 - 27 May 2015 (pp. 2437-2440). [7169177] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2015.7169177