An ultra low energy, 128 kbit 6T SRAM in 90 nm LP CMOS with energy consumption of 4.4 pJ/access, operating at 80 MHz for the wireless sensor applications is developed. The variability resilient and low power techniques developed include innovation in the local architecture with the use of local read/write assist circuitry. The energy-efficient hierarchical bit-lines structure includes low swing global bit-lines and VDD/2 pre-charged short local bit-lines. The innovative Multi-Sized SA redundancy (MS-SA-R) calibration technique for the global read sense amplifiers of the SRAM not only adds to the variability resilience but also yields maximum energy reduction compared with existing calibration techniques.
Sharma, V., Cosemans, S., Ashouei, M., Huisken, J., Catthoor, F., & Dehaene, W. (2011). A 4.4 pJ/Access 80 MHz, 128 kbit variability resilient SRAM with multi-sized sense amplifier redundancy. IEEE Journal of Solid-State Circuits, 46(10), 2416 -2430. https://doi.org/10.1109/JSSC.2011.2159056