A 4.3fJ/Conversion-Step 6440μm2 All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse

Haoming Xin; Kevin Pelzers; Peter Baltus; Eugenio Cantatore; Pieter Harpe

doi:10.1109/VLSICircuits18222.2020.9162817

A 4.3fJ/Conversion-Step 6440μm² All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

An ultra-low power all-dynamic capacitance-to-digital converter (CDC) that exploits a novel charge reuse technique is proposed, achieving a FoM as low as 4.3fJ/conv-step, which is >3× better than the state-of-the-art. It supports an inherent scaling of power vs. speed with a minimum power of only 44pW and a compact chip area of 6440μm².

Original language	English
Title of host publication	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	2
ISBN (Electronic)	9781728199429
DOIs	https://doi.org/10.1109/VLSICircuits18222.2020.9162817
Publication status	Published - Jun 2020
Event	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Honolulu, United States Duration: 16 Jun 2020 → 19 Jun 2020

Conference

Conference	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020
Country/Territory	United States
City	Honolulu
Period	16/06/20 → 19/06/20

Funding

Acknowledgements This project (PHOENIX) has received funding from the EU’s Horizon 2020 research and innovation programme under grant agreement No 665347. References

Access to Document

10.1109/VLSICircuits18222.2020.9162817

Cite this

Xin, H., Pelzers, K., Baltus, P., Cantatore, E., & Harpe, P. (2020). A 4.3fJ/Conversion-Step 6440μm² All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse. In 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings Article 9162817 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VLSICircuits18222.2020.9162817

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abstract = "An ultra-low power all-dynamic capacitance-to-digital converter (CDC) that exploits a novel charge reuse technique is proposed, achieving a FoM as low as 4.3fJ/conv-step, which is >3{\texttimes} better than the state-of-the-art. It supports an inherent scaling of power vs. speed with a minimum power of only 44pW and a compact chip area of 6440μm2.",

author = "Haoming Xin and Kevin Pelzers and Peter Baltus and Eugenio Cantatore and Pieter Harpe",

year = "2020",

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doi = "10.1109/VLSICircuits18222.2020.9162817",

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booktitle = "2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings",

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Xin, H, Pelzers, K , Baltus, P , Cantatore, E & Harpe, P 2020, A 4.3fJ/Conversion-Step 6440μm² All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse. in 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings., 9162817, Institute of Electrical and Electronics Engineers, 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, United States, 16/06/20. https://doi.org/10.1109/VLSICircuits18222.2020.9162817

A 4.3fJ/Conversion-Step 6440μm² All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse. / Xin, Haoming; Pelzers, Kevin ; Baltus, Peter et al.
2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings. Institute of Electrical and Electronics Engineers, 2020. 9162817.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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