A 40-GHz Phase-Locked Loop Front-End for 60-GHz Transceivers in 65nm CMOS

H.M. Cheema; R. Mahmoudi; A.H.M. Roermund, van

doi:10.1109/APCCAS.2010.5774963

A 40-GHz Phase-Locked Loop Front-End for 60-GHz Transceivers in 65nm CMOS

H.M. Cheema, R. Mahmoudi, A.H.M. Roermund, van

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

174 Downloads (Pure)

Abstract

A phase-locked loop front-end including a LC voltage controlled oscillator and an I-Q injection locked frequency divider is presented. The operation ranges of the VCO and ILFD are aligned by co-designing the tank, specifically the tunable varactors. The total locking range of the front-end is 37.6 to 42.2 GHz which corresponds to a down-conversion range from 56.4 to 63.3 GHz at 60 GHz, thus covering the complete ISM band. The front-end phase noise for a VCO frequency of 39.8 GHz is -102 dBc/Hz at 1 MHz offset. The DC power consumption of the VCO and Q-ILFD is 6mW and 9mW from a 1.2 V supply, respectively. Implemented in a bulk CMOS 65nm technology, the circuit occupies an area of 0.7 × 0.5 mm2.

Original language	English
Title of host publication	Proceedings of 2010 IEEE Asia Pacific Conference on Circuits and Systems(APCCAS), 6-9 December 2010, Kuala Lumpur, Malaysia
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	967-970
ISBN (Print)	978-1-4244-7454-7
DOIs	https://doi.org/10.1109/APCCAS.2010.5774963
Publication status	Published - 2010

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Cheema, H. M., Mahmoudi, R., & Roermund, van, A. H. M. (2010). A 40-GHz Phase-Locked Loop Front-End for 60-GHz Transceivers in 65nm CMOS. In Proceedings of 2010 IEEE Asia Pacific Conference on Circuits and Systems(APCCAS), 6-9 December 2010, Kuala Lumpur, Malaysia (pp. 967-970). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/APCCAS.2010.5774963

@inproceedings{3cbb7a8045f74f77b249e110b13696fd,

title = "A 40-GHz Phase-Locked Loop Front-End for 60-GHz Transceivers in 65nm CMOS",

abstract = "A phase-locked loop front-end including a LC voltage controlled oscillator and an I-Q injection locked frequency divider is presented. The operation ranges of the VCO and ILFD are aligned by co-designing the tank, specifically the tunable varactors. The total locking range of the front-end is 37.6 to 42.2 GHz which corresponds to a down-conversion range from 56.4 to 63.3 GHz at 60 GHz, thus covering the complete ISM band. The front-end phase noise for a VCO frequency of 39.8 GHz is -102 dBc/Hz at 1 MHz offset. The DC power consumption of the VCO and Q-ILFD is 6mW and 9mW from a 1.2 V supply, respectively. Implemented in a bulk CMOS 65nm technology, the circuit occupies an area of 0.7 × 0.5 mm2.",

author = "H.M. Cheema and R. Mahmoudi and {Roermund, van}, A.H.M.",

year = "2010",

doi = "10.1109/APCCAS.2010.5774963",

language = "English",

isbn = "978-1-4244-7454-7",

pages = "967--970",

booktitle = "Proceedings of 2010 IEEE Asia Pacific Conference on Circuits and Systems(APCCAS), 6-9 December 2010, Kuala Lumpur, Malaysia",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Cheema, HM, Mahmoudi, R & Roermund, van, AHM 2010, A 40-GHz Phase-Locked Loop Front-End for 60-GHz Transceivers in 65nm CMOS. in Proceedings of 2010 IEEE Asia Pacific Conference on Circuits and Systems(APCCAS), 6-9 December 2010, Kuala Lumpur, Malaysia. Institute of Electrical and Electronics Engineers, Piscataway, pp. 967-970. https://doi.org/10.1109/APCCAS.2010.5774963

A 40-GHz Phase-Locked Loop Front-End for 60-GHz Transceivers in 65nm CMOS. / Cheema, H.M.; Mahmoudi, R.; Roermund, van, A.H.M.

Proceedings of 2010 IEEE Asia Pacific Conference on Circuits and Systems(APCCAS), 6-9 December 2010, Kuala Lumpur, Malaysia. Piscataway : Institute of Electrical and Electronics Engineers, 2010. p. 967-970.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 40-GHz Phase-Locked Loop Front-End for 60-GHz Transceivers in 65nm CMOS

AU - Cheema, H.M.

AU - Mahmoudi, R.

AU - Roermund, van, A.H.M.

PY - 2010

Y1 - 2010

N2 - A phase-locked loop front-end including a LC voltage controlled oscillator and an I-Q injection locked frequency divider is presented. The operation ranges of the VCO and ILFD are aligned by co-designing the tank, specifically the tunable varactors. The total locking range of the front-end is 37.6 to 42.2 GHz which corresponds to a down-conversion range from 56.4 to 63.3 GHz at 60 GHz, thus covering the complete ISM band. The front-end phase noise for a VCO frequency of 39.8 GHz is -102 dBc/Hz at 1 MHz offset. The DC power consumption of the VCO and Q-ILFD is 6mW and 9mW from a 1.2 V supply, respectively. Implemented in a bulk CMOS 65nm technology, the circuit occupies an area of 0.7 × 0.5 mm2.

AB - A phase-locked loop front-end including a LC voltage controlled oscillator and an I-Q injection locked frequency divider is presented. The operation ranges of the VCO and ILFD are aligned by co-designing the tank, specifically the tunable varactors. The total locking range of the front-end is 37.6 to 42.2 GHz which corresponds to a down-conversion range from 56.4 to 63.3 GHz at 60 GHz, thus covering the complete ISM band. The front-end phase noise for a VCO frequency of 39.8 GHz is -102 dBc/Hz at 1 MHz offset. The DC power consumption of the VCO and Q-ILFD is 6mW and 9mW from a 1.2 V supply, respectively. Implemented in a bulk CMOS 65nm technology, the circuit occupies an area of 0.7 × 0.5 mm2.

U2 - 10.1109/APCCAS.2010.5774963

DO - 10.1109/APCCAS.2010.5774963

M3 - Conference contribution

SN - 978-1-4244-7454-7

SP - 967

EP - 970

BT - Proceedings of 2010 IEEE Asia Pacific Conference on Circuits and Systems(APCCAS), 6-9 December 2010, Kuala Lumpur, Malaysia

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

A 40-GHz Phase-Locked Loop Front-End for 60-GHz Transceivers in 65nm CMOS

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