A 40-GHz phase-locked loop for 60-GHz sliding-IF transceivers in 65nm CMOS

Hammad M. Cheema, Reza Mahmoudi, Paul T.M. Van Zeijl, Arthur Van Roermund

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

7 Citations (Scopus)

Abstract

This paper presents a 40 GHz phase-locked loop as an enabling component for sliding-IF 60 GHz transceivers. The PLL front-end includes, a 40 GHz LC voltage controlled oscillator (VCO) and a quadrature injection locked frequency divider (ILFD), which are tuned simultaneously to align their tuning and locking range, respectively. The PLL back-end consists of an optimized divider chain, PFD, CP and a second-order passive loop filter integrated on chip. The PLL can be locked from 38.2 to 43.6 GHz corresponding to a down-conversion range of 57.3 to 65.4 GHz, thus covering all IEEE 802.15.3c channels. The phase noise for a 40.2 GHz output is - 89.7, -94 and -112 dBc/Hz at 1 MHz, 4 MHz and 10 MHz offsets, respectively. The settling time is lower than 2μsec and reference spurs are lower than -42dB. Implemented in a 65nm bulk CMOS technology, the PLL consumes 22.8 mW, excluding buffers, from a 1.2 V supply and occupies 1.67×0.745 mm2 silicon area.

Original languageEnglish
Title of host publication2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages193-196
Number of pages4
DOIs
Publication statusPublished - 2010
Event6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China
Duration: 8 Nov 201010 Nov 2010
Conference number: 6
http://www.asscc.org/2010/

Conference

Conference6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Abbreviated titleA-SSCC 2010
Country/TerritoryChina
CityBeijing
Period8/11/1010/11/10
Internet address

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