A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

Shima Sedighiani; Kamlesh Singh; Roel Jordans; Pieter Harpe; Jose Pineda de Gyvez

doi:10.1109/TCSII.2023.3238961

A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

Shima Sedighiani (Corresponding author), Kamlesh Singh, Roel Jordans, Pieter Harpe, Jose Pineda de Gyvez

Research output: Contribution to journal › Article › Academic › peer-review

1 Citation (Scopus)

87 Downloads (Pure)

Abstract

Data-retention flip-flops (DR-FF) provide an efficient state retention capability for any processor with frequent active-to-sleep mode transitions. This brief proposes new ultra-low-power balloon-based DR-FFs operating over a wide supply voltage range achieving a sleep mode power consumption as low as 380fW, an improvement of 185× over the previously reported CMOS DR-FFs. The proposed DR-FFs have significantly lower transition mode energy consumption compared to prior-art non-volatile DR-FFs (> 18×). The proposed DR-FFs consume the lowest total energy (sleep, store and restore modes) for sleep mode times less than 520 ms. Additionally, the designed DR-FFs are comparable with most of the NV-FFs in literature for sleep times of up to 100 s, while eliminating the drawbacks of Non-volatile data retention FFs (higher/multiple supplies, integration/endurance issues).

Original language	English
Article number	10024364
Pages (from-to)	2650-2654
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	70
Issue number	7
DOIs	https://doi.org/10.1109/TCSII.2023.3238961
Publication status	Published - Jul 2023

Keywords

data/state retention
Delays
dynamic leakage suppression
Energy consumption
Flip-flop
Inverters
Latches
Power demand
Standards
Transistors
ultra-low power

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/TCSII.2023.3238961

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Cite this

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title = "A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods",

abstract = "Data-retention flip-flops (DR-FF) provide an efficient state retention capability for any processor with frequent active-to-sleep mode transitions. This brief proposes new ultra-low-power balloon-based DR-FFs operating over a wide supply voltage range achieving a sleep mode power consumption as low as 380fW, an improvement of 185× over the previously reported CMOS DR-FFs. The proposed DR-FFs have significantly lower transition mode energy consumption compared to prior-art non-volatile DR-FFs (> 18×). The proposed DR-FFs consume the lowest total energy (sleep, store and restore modes) for sleep mode times less than 520 ms. Additionally, the designed DR-FFs are comparable with most of the NV-FFs in literature for sleep times of up to 100 s, while eliminating the drawbacks of Non-volatile data retention FFs (higher/multiple supplies, integration/endurance issues).",

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AU - Harpe, Pieter

AU - de Gyvez, Jose Pineda

PY - 2023/7

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N2 - Data-retention flip-flops (DR-FF) provide an efficient state retention capability for any processor with frequent active-to-sleep mode transitions. This brief proposes new ultra-low-power balloon-based DR-FFs operating over a wide supply voltage range achieving a sleep mode power consumption as low as 380fW, an improvement of 185× over the previously reported CMOS DR-FFs. The proposed DR-FFs have significantly lower transition mode energy consumption compared to prior-art non-volatile DR-FFs (> 18×). The proposed DR-FFs consume the lowest total energy (sleep, store and restore modes) for sleep mode times less than 520 ms. Additionally, the designed DR-FFs are comparable with most of the NV-FFs in literature for sleep times of up to 100 s, while eliminating the drawbacks of Non-volatile data retention FFs (higher/multiple supplies, integration/endurance issues).

AB - Data-retention flip-flops (DR-FF) provide an efficient state retention capability for any processor with frequent active-to-sleep mode transitions. This brief proposes new ultra-low-power balloon-based DR-FFs operating over a wide supply voltage range achieving a sleep mode power consumption as low as 380fW, an improvement of 185× over the previously reported CMOS DR-FFs. The proposed DR-FFs have significantly lower transition mode energy consumption compared to prior-art non-volatile DR-FFs (> 18×). The proposed DR-FFs consume the lowest total energy (sleep, store and restore modes) for sleep mode times less than 520 ms. Additionally, the designed DR-FFs are comparable with most of the NV-FFs in literature for sleep times of up to 100 s, while eliminating the drawbacks of Non-volatile data retention FFs (higher/multiple supplies, integration/endurance issues).

KW - data/state retention

KW - Delays

KW - dynamic leakage suppression

KW - Energy consumption

KW - Flip-flop

KW - Inverters

KW - Latches

KW - Power demand

KW - Standards

KW - Transistors

KW - ultra-low power

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ER -

A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

Abstract

Keywords

UN SDGs

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