In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72µW with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9µW.
|Title of host publication||Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 1 Apr 2011|
Zhang, Y., Chen, S., Kiyani, N. F., Dolmans, G., Huisken, J., Büsze, B., ... Groot, de, H. W. H. (2011). A 3.72μW ultra-low power digital baseband for wake-up radios. In Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan (pp. 1-4). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VDAT.2011.5783586