Abstract
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 1-4 |
| ISBN (Print) | 978-1-4244-8500-0 |
| DOIs | |
| Publication status | Published - 1 Apr 2011 |
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A 3.72μW ultra-low power digital baseband for wake-up radios. / Zhang, Y.; Chen, Sijie; Kiyani, N.F.; Dolmans, G.; Huisken, J.; Büsze, B.; Harpe, P.J.A.; Meijs, van der, N.P.; Groot, de, H.W.H.
Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan. Piscataway : Institute of Electrical and Electronics Engineers, 2011. p. 1-4.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - A 3.72μW ultra-low power digital baseband for wake-up radios
AU - Zhang, Y.
AU - Chen, Sijie
AU - Kiyani, N.F.
AU - Dolmans, G.
AU - Huisken, J.
AU - Büsze, B.
AU - Harpe, P.J.A.
AU - Meijs, van der, N.P.
AU - Groot, de, H.W.H.
PY - 2011/4/1
Y1 - 2011/4/1
N2 - In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72µW with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9µW.
AB - In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72µW with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9µW.
U2 - 10.1109/VDAT.2011.5783586
DO - 10.1109/VDAT.2011.5783586
M3 - Conference contribution
SN - 978-1-4244-8500-0
SP - 1
EP - 4
BT - Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan
PB - Institute of Electrical and Electronics Engineers
CY - Piscataway
ER -