A 3.72μW ultra-low power digital baseband for wake-up radios

Y. Zhang, Sijie Chen, N.F. Kiyani, G. Dolmans, J. Huisken, B. Büsze, P.J.A. Harpe, N.P. Meijs, van der, H.W.H. Groot, de

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13 Citations (Scopus)
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Abstract

In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72µW with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9µW.
Original languageEnglish
Title of host publicationProceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages1-4
ISBN (Print)978-1-4244-8500-0
DOIs
Publication statusPublished - 1 Apr 2011

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    Zhang, Y., Chen, S., Kiyani, N. F., Dolmans, G., Huisken, J., Büsze, B., ... Groot, de, H. W. H. (2011). A 3.72μW ultra-low power digital baseband for wake-up radios. In Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan (pp. 1-4). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VDAT.2011.5783586