Abstract
In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72µW with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9µW.
Original language | English |
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Title of host publication | Proceedings of the 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-28 April 2011, Hsinchu, Taiwan |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 1-4 |
ISBN (Print) | 978-1-4244-8500-0 |
DOIs | |
Publication status | Published - 1 Apr 2011 |