A 36 GHz to 144 GHz Frequency Upconverter Employing a Current Reuse Frequency Doubler with a Differential to Differential Transformer

Johan Holmstedt; Vojkan Vidojkovic; Rainier Van Dommele; Dusan Milosevic; Peter Baltus

doi:10.1109/ICECS61496.2024.10848792

A 36 GHz to 144 GHz Frequency Upconverter Employing a Current Reuse Frequency Doubler with a Differential to Differential Transformer

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This work presents a 36 GHz to 144 GHz frequency up converter, consisting of two cascaded frequency doublers. To improve efficiency and robustness, the frequency doublers are based on a current reuse principle and employe a symmetric transformer. A voltage conversion gain of 0 dB and very low phase noise are achieved while consuming only 3.2 milliwatts from a 0.9V supply. The chip is implemented in 28 nm bulk CMOS and occupies a core area of 400x190um.

Original language	English
Title of host publication	2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	4
ISBN (Electronic)	979-8-3503-7720-0
DOIs	https://doi.org/10.1109/ICECS61496.2024.10848792
Publication status	Published - 28 Jan 2025
Event	31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024 - Nancy, France Duration: 18 Nov 2024 → 20 Nov 2024

Conference

Conference	31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024
Country/Territory	France
City	Nancy
Period	18/11/24 → 20/11/24

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

Keywords

D-band
Frequency doubler
high conversion gain

Access to Document

10.1109/ICECS61496.2024.10848792

pdfFinal published version, 1.07 MBLicence: TAVERNE

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Holmstedt, J., Vidojkovic, V., Van Dommele, R., Milosevic, D., & Baltus, P. (2025). A 36 GHz to 144 GHz Frequency Upconverter Employing a Current Reuse Frequency Doubler with a Differential to Differential Transformer. In 2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024 Article 10848792 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICECS61496.2024.10848792

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abstract = "This work presents a 36 GHz to 144 GHz frequency up converter, consisting of two cascaded frequency doublers. To improve efficiency and robustness, the frequency doublers are based on a current reuse principle and employe a symmetric transformer. A voltage conversion gain of 0 dB and very low phase noise are achieved while consuming only 3.2 milliwatts from a 0.9V supply. The chip is implemented in 28 nm bulk CMOS and occupies a core area of 400x190um.",

keywords = "D-band, Frequency doubler, high conversion gain",

author = "Johan Holmstedt and Vojkan Vidojkovic and \{Van Dommele\}, Rainier and Dusan Milosevic and Peter Baltus",

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year = "2025",

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day = "28",

doi = "10.1109/ICECS61496.2024.10848792",

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Holmstedt, J , Vidojkovic, V , Van Dommele, R , Milosevic, D & Baltus, P 2025, A 36 GHz to 144 GHz Frequency Upconverter Employing a Current Reuse Frequency Doubler with a Differential to Differential Transformer. in 2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024., 10848792, Institute of Electrical and Electronics Engineers, 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024, Nancy, France, 18/11/24. https://doi.org/10.1109/ICECS61496.2024.10848792

A 36 GHz to 144 GHz Frequency Upconverter Employing a Current Reuse Frequency Doubler with a Differential to Differential Transformer. / Holmstedt, Johan ; Vidojkovic, Vojkan ; Van Dommele, Rainier et al.
2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024. Institute of Electrical and Electronics Engineers, 2025. 10848792.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Holmstedt, Johan

AU - Vidojkovic, Vojkan

AU - Van Dommele, Rainier

AU - Milosevic, Dusan

AU - Baltus, Peter

PY - 2025/1/28

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N2 - This work presents a 36 GHz to 144 GHz frequency up converter, consisting of two cascaded frequency doublers. To improve efficiency and robustness, the frequency doublers are based on a current reuse principle and employe a symmetric transformer. A voltage conversion gain of 0 dB and very low phase noise are achieved while consuming only 3.2 milliwatts from a 0.9V supply. The chip is implemented in 28 nm bulk CMOS and occupies a core area of 400x190um.

AB - This work presents a 36 GHz to 144 GHz frequency up converter, consisting of two cascaded frequency doublers. To improve efficiency and robustness, the frequency doublers are based on a current reuse principle and employe a symmetric transformer. A voltage conversion gain of 0 dB and very low phase noise are achieved while consuming only 3.2 milliwatts from a 0.9V supply. The chip is implemented in 28 nm bulk CMOS and occupies a core area of 400x190um.

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KW - Frequency doubler

KW - high conversion gain

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DO - 10.1109/ICECS61496.2024.10848792

M3 - Conference contribution

AN - SCOPUS:85217617184

BT - 2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024

PB - Institute of Electrical and Electronics Engineers

T2 - 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024

Y2 - 18 November 2024 through 20 November 2024

ER -

Holmstedt J , Vidojkovic V , Van Dommele R , Milosevic D , Baltus P. A 36 GHz to 144 GHz Frequency Upconverter Employing a Current Reuse Frequency Doubler with a Differential to Differential Transformer. In 2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024. Institute of Electrical and Electronics Engineers. 2025. 10848792 doi: 10.1109/ICECS61496.2024.10848792

A 36 GHz to 144 GHz Frequency Upconverter Employing a Current Reuse Frequency Doubler with a Differential to Differential Transformer

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