A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

P. Cenci; M. Bolatkale; R. Rutten; M. Ganzerli; G. Lassche; K. Makinwa; L. Breems

doi:10.23919/VLSIC.2019.8778176

A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

P. Cenci
, M. Bolatkale
, R. Rutten
, M. Ganzerli
, G. Lassche
, K. Makinwa
, L. Breems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

22 Citations (Scopus)

Abstract

This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.

Original language	English
Title of host publication	2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	C230-C231
Number of pages	2
ISBN (Electronic)	978-4-86348-720-8
DOIs	https://doi.org/10.23919/VLSIC.2019.8778176
Publication status	Published - 1 Jun 2019
Event	33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan, Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019

Conference

Conference	33rd Symposium on VLSI Circuits, VLSI Circuits 2019
Country/Territory	Japan
City	Kyoto
Period	9/06/19 → 14/06/19

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.23919/VLSIC.2019.8778176

Cite this

Cenci, P., Bolatkale, M., Rutten, R., Ganzerli, M., Lassche, G., Makinwa, K., & Breems, L. (2019). A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (pp. C230-C231). Article 8778176 Institute of Electrical and Electronics Engineers. https://doi.org/10.23919/VLSIC.2019.8778176

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title = "A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS",

abstract = "This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.",

author = "P. Cenci and M. Bolatkale and R. Rutten and M. Ganzerli and G. Lassche and K. Makinwa and L. Breems",

year = "2019",

month = jun,

day = "1",

doi = "10.23919/VLSIC.2019.8778176",

language = "English",

pages = "C230--C231",

booktitle = "2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers",

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Cenci, P, Bolatkale, M, Rutten, R, Ganzerli, M, Lassche, G, Makinwa, K & Breems, L 2019, A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. in 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers., 8778176, Institute of Electrical and Electronics Engineers, Piscataway, pp. C230-C231, 33rd Symposium on VLSI Circuits, VLSI Circuits 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIC.2019.8778176

A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. / Cenci, P.; Bolatkale, M.; Rutten, R. et al.
2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Piscataway: Institute of Electrical and Electronics Engineers, 2019. p. C230-C231 8778176.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Cenci, P.

AU - Bolatkale, M.

AU - Rutten, R.

AU - Ganzerli, M.

AU - Lassche, G.

AU - Makinwa, K.

AU - Breems, L.

PY - 2019/6/1

Y1 - 2019/6/1

N2 - This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.

AB - This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.

UR - https://www.scopus.com/pages/publications/85073894417

U2 - 10.23919/VLSIC.2019.8778176

DO - 10.23919/VLSIC.2019.8778176

M3 - Conference contribution

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BT - 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 33rd Symposium on VLSI Circuits, VLSI Circuits 2019

Y2 - 9 June 2019 through 14 June 2019

ER -

A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

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