A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

P. Cenci, M. Bolatkale, R. Rutten, M. Ganzerli, G. Lassche, K. Makinwa, L. Breems

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.

Original languageEnglish
Title of host publication2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
PagesC230-C231
Number of pages2
ISBN (Electronic)978-4-86348-720-8
DOIs
Publication statusPublished - 1 Jun 2019
Event33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan
Duration: 9 Jun 201914 Jun 2019

Conference

Conference33rd Symposium on VLSI Circuits, VLSI Circuits 2019
CountryJapan
CityKyoto
Period9/06/1914/06/19

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Cite this

Cenci, P., Bolatkale, M., Rutten, R., Ganzerli, M., Lassche, G., Makinwa, K., & Breems, L. (2019). A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (pp. C230-C231). [8778176] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.23919/VLSIC.2019.8778176
Cenci, P. ; Bolatkale, M. ; Rutten, R. ; Ganzerli, M. ; Lassche, G. ; Makinwa, K. ; Breems, L. / A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Piscataway : Institute of Electrical and Electronics Engineers, 2019. pp. C230-C231
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abstract = "This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.",
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Cenci, P, Bolatkale, M, Rutten, R, Ganzerli, M, Lassche, G, Makinwa, K & Breems, L 2019, A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. in 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers., 8778176, Institute of Electrical and Electronics Engineers, Piscataway, pp. C230-C231, 33rd Symposium on VLSI Circuits, VLSI Circuits 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIC.2019.8778176

A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. / Cenci, P.; Bolatkale, M.; Rutten, R.; Ganzerli, M.; Lassche, G.; Makinwa, K.; Breems, L.

2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Piscataway : Institute of Electrical and Electronics Engineers, 2019. p. C230-C231 8778176.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AB - This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.

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Cenci P, Bolatkale M, Rutten R, Ganzerli M, Lassche G, Makinwa K et al. A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Piscataway: Institute of Electrical and Electronics Engineers. 2019. p. C230-C231. 8778176 https://doi.org/10.23919/VLSIC.2019.8778176