A 32.2-GHz Full Adder in InP DHBT Technology

Yi Zhang, Xiaopeng Li, Youtao Zhang, Ying Zhang, Yufeng Guo, Zhonghua Liu, Hao Gao

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

An ultra-high speed 1bit full adder based on indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology is presented. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce the power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350mW.
Original languageEnglish
Title of host publication2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages3
ISBN (Electronic)978-1-7281-2496-4
DOIs
Publication statusPublished - Aug 2019
Event2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) - Nanjing, China
Duration: 28 Aug 201930 Aug 2019

Conference

Conference2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
CountryChina
CityNanjing
Period28/08/1930/08/19

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