A 32.2-GHz Full Adder in InP DHBT Technology

Yi Zhang; Xiaopeng Li; Youtao Zhang; Ying Zhang; Yufeng Guo; Zhonghua Liu; Hao Gao

doi:10.1109/RFIT.2019.8929166

A 32.2-GHz Full Adder in InP DHBT Technology

Yi Zhang, Xiaopeng Li, Youtao Zhang, Ying Zhang, Yufeng Guo, Zhonghua Liu, Hao Gao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

An ultra-high speed 1bit full adder based on indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology is presented. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce the power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350mW.

Original language	English
Title of host publication	2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	3
ISBN (Electronic)	978-1-7281-2496-4
DOIs	https://doi.org/10.1109/RFIT.2019.8929166
Publication status	Published - Aug 2019
Event	2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) - Nanjing, China Duration: 28 Aug 2019 → 30 Aug 2019

Conference

Conference	2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
Country	China
City	Nanjing
Period	28/08/19 → 30/08/19

Access to Document

10.1109/RFIT.2019.8929166

Fingerprint Dive into the research topics of 'A 32.2-GHz Full Adder in InP DHBT Technology'. Together they form a unique fingerprint.

Cite this

@inproceedings{aadbec561bd940fc8696b36fe1f6be73,

title = "A 32.2-GHz Full Adder in InP DHBT Technology",

abstract = "An ultra-high speed 1bit full adder based on indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology is presented. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce the power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350mW.",

author = "Yi Zhang and Xiaopeng Li and Youtao Zhang and Ying Zhang and Yufeng Guo and Zhonghua Liu and Hao Gao",

year = "2019",

month = aug,

doi = "10.1109/RFIT.2019.8929166",

language = "English",

booktitle = "2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) ; Conference date: 28-08-2019 Through 30-08-2019",

}

Zhang, Y, Li, X, Zhang, Y, Zhang, Y, Guo, Y, Liu, Z & Gao, H 2019, A 32.2-GHz Full Adder in InP DHBT Technology. in 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)., 8929166, Institute of Electrical and Electronics Engineers, Piscataway, 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Nanjing, China, 28/08/19. https://doi.org/10.1109/RFIT.2019.8929166

A 32.2-GHz Full Adder in InP DHBT Technology. / Zhang, Yi; Li, Xiaopeng; Zhang, Youtao; Zhang, Ying; Guo, Yufeng; Liu, Zhonghua; Gao, Hao.

2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT). Piscataway : Institute of Electrical and Electronics Engineers, 2019. 8929166.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 32.2-GHz Full Adder in InP DHBT Technology

AU - Zhang, Yi

AU - Li, Xiaopeng

AU - Zhang, Youtao

AU - Zhang, Ying

AU - Guo, Yufeng

AU - Liu, Zhonghua

AU - Gao, Hao

PY - 2019/8

Y1 - 2019/8

N2 - An ultra-high speed 1bit full adder based on indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology is presented. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce the power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350mW.

AB - An ultra-high speed 1bit full adder based on indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology is presented. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce the power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350mW.

UR - http://www.scopus.com/inward/record.url?scp=85078047559&partnerID=8YFLogxK

U2 - 10.1109/RFIT.2019.8929166

DO - 10.1109/RFIT.2019.8929166

M3 - Conference contribution

BT - 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

Y2 - 28 August 2019 through 30 August 2019

ER -

A 32.2-GHz Full Adder in InP DHBT Technology

Abstract

Conference

Access to Document

Other files and links

Cite this