A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS

P.J.A. Harpe; C. Zhou; Xiaoyan Wang; G. Dolmans; H.W.H. Groot, de

doi:10.1109/ISSCC.2010.5433967

A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS

P.J.A. Harpe
, C. Zhou
, Xiaoyan Wang
, G. Dolmans
, H.W.H. Groot, de

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

88 Citations (Scopus)

5 Downloads (Pure)

Abstract

An 8 b SAR ADC is presented. The 90 nm CMOS prototype achieves an ENOB of 7.8 b at a sampling frequency of 10.24 MS/S. The use of asynchronous dynamic CMOS logic, custom-designed capacitors, an internal common-mode shift and low-leakage design techniques results in a power consumption of 69 Â¿W from a 1 V supply. The corresponding FoM equals 30 fJ/Conversion-step and is maintained down to 10 kS/s.

Original language	English
Title of host publication	Proceedings of the IEEE International Solid-State Circuits Conference 2010 (ISSCC 2010), 7-11 February 2010, Pennsylvania
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	388-389
ISBN (Print)	978-1-4244-6033-5
DOIs	https://doi.org/10.1109/ISSCC.2010.5433967
Publication status	Published - 2010

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10.1109/ISSCC.2010.5433967

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Harpe, P. J. A., Zhou, C., Wang, X., Dolmans, G., & Groot, de, H. W. H. (2010). A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS. In Proceedings of the IEEE International Solid-State Circuits Conference 2010 (ISSCC 2010), 7-11 February 2010, Pennsylvania (pp. 388-389). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSCC.2010.5433967

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title = "A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS",

abstract = "An 8 b SAR ADC is presented. The 90 nm CMOS prototype achieves an ENOB of 7.8 b at a sampling frequency of 10.24 MS/S. The use of asynchronous dynamic CMOS logic, custom-designed capacitors, an internal common-mode shift and low-leakage design techniques results in a power consumption of 69 {\^A}¿W from a 1 V supply. The corresponding FoM equals 30 fJ/Conversion-step and is maintained down to 10 kS/s.",

author = "P.J.A. Harpe and C. Zhou and Xiaoyan Wang and G. Dolmans and \{Groot, de\}, H.W.H.",

year = "2010",

doi = "10.1109/ISSCC.2010.5433967",

language = "English",

isbn = "978-1-4244-6033-5",

pages = "388--389",

booktitle = "Proceedings of the IEEE International Solid-State Circuits Conference 2010 (ISSCC 2010), 7-11 February 2010, Pennsylvania",

publisher = "Institute of Electrical and Electronics Engineers",

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Harpe, PJA, Zhou, C, Wang, X, Dolmans, G & Groot, de, HWH 2010, A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS. in Proceedings of the IEEE International Solid-State Circuits Conference 2010 (ISSCC 2010), 7-11 February 2010, Pennsylvania. Institute of Electrical and Electronics Engineers, Piscataway, pp. 388-389. https://doi.org/10.1109/ISSCC.2010.5433967

A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS. / Harpe, P.J.A.; Zhou, C.; Wang, Xiaoyan et al.
Proceedings of the IEEE International Solid-State Circuits Conference 2010 (ISSCC 2010), 7-11 February 2010, Pennsylvania. Piscataway: Institute of Electrical and Electronics Engineers, 2010. p. 388-389.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - An 8 b SAR ADC is presented. The 90 nm CMOS prototype achieves an ENOB of 7.8 b at a sampling frequency of 10.24 MS/S. The use of asynchronous dynamic CMOS logic, custom-designed capacitors, an internal common-mode shift and low-leakage design techniques results in a power consumption of 69 Â¿W from a 1 V supply. The corresponding FoM equals 30 fJ/Conversion-step and is maintained down to 10 kS/s.

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A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS

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