A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS

P.J.A. Harpe, C. Zhou, Xiaoyan Wang, G. Dolmans, H.W.H. Groot, de

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

87 Citations (Scopus)
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An 8 b SAR ADC is presented. The 90 nm CMOS prototype achieves an ENOB of 7.8 b at a sampling frequency of 10.24 MS/S. The use of asynchronous dynamic CMOS logic, custom-designed capacitors, an internal common-mode shift and low-leakage design techniques results in a power consumption of 69 ¿W from a 1 V supply. The corresponding FoM equals 30 fJ/Conversion-step and is maintained down to 10 kS/s.
Original languageEnglish
Title of host publicationProceedings of the IEEE International Solid-State Circuits Conference 2010 (ISSCC 2010), 7-11 February 2010, Pennsylvania
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)978-1-4244-6033-5
Publication statusPublished - 2010


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