A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR

Martijn Timmermans; Marco Fattori; Pieter Harpe; Yao-Hong Liu; Eugenio Cantatore

doi:10.23919/VLSITechnologyandCir57934.2023.10185322

A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR

Martijn Timmermans, Marco Fattori, Pieter Harpe, Yao-Hong Liu, Eugenio Cantatore

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

6 Downloads (Pure)

Abstract

This paper presents a level crossing ADC (LC-ADC) for biomedical applications. The ADC uses dynamically biased comparators, which require minimal power when the input voltage is far away from a decision threshold. This results in >10x better power efficiency compared to prior LC-ADCs when converting sparse signals. In a 16 kHz bandwidth, the LC-ADC achieves a 61.4 dB SNDR resulting in an efficiency of 3 fJ/conv.step for sparse input signals.

Original language	English
Title of host publication	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Publisher	Institute of Electrical and Electronics Engineers
Chapter	C18-1
Number of pages	2
ISBN (Electronic)	978-4-86348-806-9
DOIs	https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185322
Publication status	Published - 24 Jul 2023
Event	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan Duration: 11 Jun 2023 → 16 Jun 2023

Conference

Conference	2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/Territory	Japan
City	Kyoto
Period	11/06/23 → 16/06/23

Bibliographical note

Funding Information:
This work is supported by the Dutch Research Council (NWO) under Project 17608.

Funding

This work is supported by the Dutch Research Council (NWO) under Project 17608.

Access to Document

10.23919/VLSITechnologyandCir57934.2023.10185322

Cite this

Timmermans, M., Fattori, M., Harpe, P., Liu, Y.-H., & Cantatore, E. (2023). A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 Article 10185322 Institute of Electrical and Electronics Engineers. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185322

@inproceedings{5bb5092529d74da39d383ac4ee12d491,

title = "A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR",

abstract = "This paper presents a level crossing ADC (LC-ADC) for biomedical applications. The ADC uses dynamically biased comparators, which require minimal power when the input voltage is far away from a decision threshold. This results in >10x better power efficiency compared to prior LC-ADCs when converting sparse signals. In a 16 kHz bandwidth, the LC-ADC achieves a 61.4 dB SNDR resulting in an efficiency of 3 fJ/conv.step for sparse input signals.",

author = "Martijn Timmermans and Marco Fattori and Pieter Harpe and Yao-Hong Liu and Eugenio Cantatore",

note = "Funding Information: This work is supported by the Dutch Research Council (NWO) under Project 17608. ; 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 ; Conference date: 11-06-2023 Through 16-06-2023",

year = "2023",

month = jul,

day = "24",

doi = "10.23919/VLSITechnologyandCir57934.2023.10185322",

language = "English",

booktitle = "2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Timmermans, M , Fattori, M , Harpe, P , Liu, Y-H & Cantatore, E 2023, A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR. in 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023., 10185322, Institute of Electrical and Electronics Engineers, 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023, Kyoto, Japan, 11/06/23. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185322

A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR. / Timmermans, Martijn ; Fattori, Marco ; Harpe, Pieter et al.
2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers, 2023. 10185322.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR

AU - Timmermans, Martijn

AU - Fattori, Marco

AU - Harpe, Pieter

AU - Liu, Yao-Hong

AU - Cantatore, Eugenio

N1 - Funding Information: This work is supported by the Dutch Research Council (NWO) under Project 17608.

PY - 2023/7/24

Y1 - 2023/7/24

N2 - This paper presents a level crossing ADC (LC-ADC) for biomedical applications. The ADC uses dynamically biased comparators, which require minimal power when the input voltage is far away from a decision threshold. This results in >10x better power efficiency compared to prior LC-ADCs when converting sparse signals. In a 16 kHz bandwidth, the LC-ADC achieves a 61.4 dB SNDR resulting in an efficiency of 3 fJ/conv.step for sparse input signals.

AB - This paper presents a level crossing ADC (LC-ADC) for biomedical applications. The ADC uses dynamically biased comparators, which require minimal power when the input voltage is far away from a decision threshold. This results in >10x better power efficiency compared to prior LC-ADCs when converting sparse signals. In a 16 kHz bandwidth, the LC-ADC achieves a 61.4 dB SNDR resulting in an efficiency of 3 fJ/conv.step for sparse input signals.

UR - http://www.scopus.com/inward/record.url?scp=85167612885&partnerID=8YFLogxK

U2 - 10.23919/VLSITechnologyandCir57934.2023.10185322

DO - 10.23919/VLSITechnologyandCir57934.2023.10185322

M3 - Conference contribution

AN - SCOPUS:85167612885

BT - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

PB - Institute of Electrical and Electronics Engineers

T2 - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023

Y2 - 11 June 2023 through 16 June 2023

ER -

Timmermans M , Fattori M , Harpe P , Liu YH , Cantatore E. A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR. In 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers. 2023. 10185322 doi: 10.23919/VLSITechnologyandCir57934.2023.10185322

A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR

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