A 28-nm CMOS 7-GS/s 6-bit DAC with DfT clock and memory reaching SFDR >50 dB Up to 1 GHz

G.I. Radulov, P.J. Quinn, A.H.M. Roermund, van

Research output: Contribution to journalArticleAcademicpeer-review

9 Citations (Scopus)
3 Downloads (Pure)


This brief presents a 7-GS/s 6-bit current-steering digital-to-analog converter (DAC) in 28-nm CMOS for VLSI System On Chip I/O embedding with an on-chip memory and clock generation circuits for wafer-sort testing. It demonstrates how Spurious Free Dynamic Range (>50) dB can be maintained up to 1 GHz, while keeping the DAC footprint small (-0.035) mm(^{mathrm {mathbf {2}}}). Several linearization techniques, such as current source cascodes with local biasing, thick-oxide output cascodes, bleeding currents, and 50% level of segmentation are validated for the first time at such very high frequencies. Testing is facilitated by means of integrating a digital front-end design-for-test scheme in 0.048 mm(^{mathrm {mathbf {2}}}). It uses a 5-kb 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7-GHz Current Mode Logic ring oscillator-type clock generator and a serial data interface enable simple testing of the DAC at reduced cost.
Original languageEnglish
Pages (from-to)1941-1945
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number9
Publication statusPublished - 2015


Dive into the research topics of 'A 28-nm CMOS 7-GS/s 6-bit DAC with DfT clock and memory reaching SFDR >50 dB Up to 1 GHz'. Together they form a unique fingerprint.

Cite this