A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC with signal-independent delta-I noise DfT scheme

G.I. Radulov, J.A. Quinn, A.H.M. Roermund, van

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This paper presents a 3.5GSps 6-bit current-steering DAC with auxiliary circuitry to assist testing in a 1V digital 28nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035mm2, making it suitable to embedding in VLSI systems, e.g. FPGA. To cope with the IC process variability, a unit element approach is generally employed. The 3 MSBs are implemented as 7 unary D/A cells and the 3 LSBs as 3 binary D/A cells, using appropriately reduced number of unit elements. Furthermore, all digital gates only make use of two basic unit blocks: a buffer and a multiplexer. For testing, a memory block of 5kbits is placed on-chip, which is externally loaded in a serial way but internally read in an 8x time-interleaved way. The memory is organized around 48 clocked 104-bit shift-registers. It keeps the resulting switching disturbances signal-independent and hence avoids inducing output non-linearity errors, even when a common power supply is shared with the DAC. This novelty allows reliable testing of the DAC core, while avoiding performance limitation risks of handling high-speed off-chip data streams. The DAC SFDR>40dB bandwidth is 0.8GHz, while the IM3
Original languageEnglish
Pages (from-to)44-53
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number1
Publication statusPublished - 2015


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