A 28 nm 2 GS/s 5-b Single-channel SAR ADC with gm-boosted StrongARM Comparator

Pierluigi Cenci, Muhammed Bolatkale, Robert Rutten, Gerard Lassche, Kofi Makinwa, Lucien Breems

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

7 Citations (Scopus)


This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMW=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.

Original languageEnglish
Title of host publicationESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages4
ISBN (Electronic)9781509050253
Publication statusPublished - 2 Nov 2017
Event43rd European Solid State Circuits Conference (ESSCIRC 2017) - Leuven, Belgium
Duration: 11 Sep 201714 Sep 2017
Conference number: 43


Conference43rd European Solid State Circuits Conference (ESSCIRC 2017)
Abbreviated titleESSCIRC 2017
Other47th European Solid-State Device Research Conference (ESSDERC 2017) & 43rd European Solid-State Circuits Conference (ESSCIRC 2017), 11-14 September 2017, Leuven, Belgium


  • 28 nm CMOS
  • Asynchronous logic
  • Bottom plate sampling
  • Gm-boosted StrongARM comparator
  • Rail-to-rail input signal
  • SAR converter
  • Single-channel


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