A 28 nm 2 GS/s 5-b Single-channel SAR ADC with gm-boosted StrongARM Comparator

Pierluigi Cenci, Muhammed Bolatkale, Robert Rutten, Gerard Lassche, Kofi Makinwa, Lucien Breems

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)

Abstract

This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMW=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.

LanguageEnglish
Title of host publicationESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages171-174
Number of pages4
ISBN (Electronic)9781509050253
DOIs
StatePublished - 2 Nov 2017
Event43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017) - Leuven, Belgium
Duration: 11 Sep 201714 Sep 2017
Conference number: 43

Conference

Conference43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017)
Abbreviated titleESSCIRC 2017
CountryBelgium
CityLeuven
Period11/09/1714/09/17

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sampling
Sampling
clocks
Clocks
CMOS
Calibration
Feedback
cycles

Keywords

  • 28 nm CMOS
  • Asynchronous logic
  • Bottom plate sampling
  • Gm-boosted StrongARM comparator
  • Rail-to-rail input signal
  • SAR converter
  • Single-channel

Cite this

Cenci, P., Bolatkale, M., Rutten, R., Lassche, G., Makinwa, K., & Breems, L. (2017). A 28 nm 2 GS/s 5-b Single-channel SAR ADC with gm-boosted StrongARM Comparator. In ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference (pp. 171-174). [8094553] Piscataway: Institute of Electrical and Electronics Engineers. DOI: 10.1109/ESSCIRC.2017.8094553
Cenci, Pierluigi ; Bolatkale, Muhammed ; Rutten, Robert ; Lassche, Gerard ; Makinwa, Kofi ; Breems, Lucien. / A 28 nm 2 GS/s 5-b Single-channel SAR ADC with gm-boosted StrongARM Comparator. ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference. Piscataway : Institute of Electrical and Electronics Engineers, 2017. pp. 171-174
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title = "A 28 nm 2 GS/s 5-b Single-channel SAR ADC with gm-boosted StrongARM Comparator",
abstract = "This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMW=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.",
keywords = "28 nm CMOS, Asynchronous logic, Bottom plate sampling, Gm-boosted StrongARM comparator, Rail-to-rail input signal, SAR converter, Single-channel",
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Cenci, P, Bolatkale, M, Rutten, R, Lassche, G, Makinwa, K & Breems, L 2017, A 28 nm 2 GS/s 5-b Single-channel SAR ADC with gm-boosted StrongARM Comparator. in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference., 8094553, Institute of Electrical and Electronics Engineers, Piscataway, pp. 171-174, 43rd IEEE European Solid State Circuits Conference (ESSCIRC 2017), Leuven, Belgium, 11/09/17. DOI: 10.1109/ESSCIRC.2017.8094553

A 28 nm 2 GS/s 5-b Single-channel SAR ADC with gm-boosted StrongARM Comparator. / Cenci, Pierluigi; Bolatkale, Muhammed; Rutten, Robert; Lassche, Gerard; Makinwa, Kofi; Breems, Lucien.

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference. Piscataway : Institute of Electrical and Electronics Engineers, 2017. p. 171-174 8094553.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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N2 - This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMW=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.

AB - This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMW=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.

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Cenci P, Bolatkale M, Rutten R, Lassche G, Makinwa K, Breems L. A 28 nm 2 GS/s 5-b Single-channel SAR ADC with gm-boosted StrongARM Comparator. In ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference. Piscataway: Institute of Electrical and Electronics Engineers. 2017. p. 171-174. 8094553. Available from, DOI: 10.1109/ESSCIRC.2017.8094553