A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

Remco C.H. van de Beek; Cicero S. Vaucher; Domine M.W. Leenaerts; Eric A.M. Klumperink; Bram Nauta

doi:10.1109/JSSC.2004.835833

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

Remco C.H. van de Beek (Corresponding author)
, Cicero S. Vaucher
, Domine M.W. Leenaerts
, Eric A.M. Klumperink
, Bram Nauta

Research output: Contribution to journal › Article › Academic › peer-review

40 Citations (Scopus)

Abstract

This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that over-comes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.

Original language	English
Article number	1347317
Pages (from-to)	1862-1872
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	39
Issue number	11
DOIs	https://doi.org/10.1109/JSSC.2004.835833
Publication status	Published - Nov 2004
Externally published	Yes

Keywords

Charge pump
Clock generation
Clock multiplication
Clock multiplier unit (CMU)
CMOS
Frequency detector
Frequency multiplication
Frequency synthesizer
High speed
Low jitter
Low noise
Phase detector
Phase frequency detector (PFD)

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10.1109/JSSC.2004.835833

Cite this

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title = "A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS",

abstract = "This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that over-comes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.",

keywords = "Charge pump, Clock generation, Clock multiplication, Clock multiplier unit (CMU), CMOS, Frequency detector, Frequency multiplication, Frequency synthesizer, High speed, Low jitter, Low noise, Phase detector, Phase frequency detector (PFD)",

author = "\{van de Beek\}, \{Remco C.H.\} and Vaucher, \{Cicero S.\} and Leenaerts, \{Domine M.W.\} and Klumperink, \{Eric A.M.\} and Bram Nauta",

year = "2004",

month = nov,

doi = "10.1109/JSSC.2004.835833",

language = "English",

volume = "39",

pages = "1862--1872",

journal = "IEEE Journal of Solid-State Circuits",

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publisher = "Institute of Electrical and Electronics Engineers",

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AU - van de Beek, Remco C.H.

AU - Vaucher, Cicero S.

AU - Leenaerts, Domine M.W.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

PY - 2004/11

Y1 - 2004/11

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AB - This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that over-comes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.

KW - Charge pump

KW - Clock generation

KW - Clock multiplication

KW - Clock multiplier unit (CMU)

KW - CMOS

KW - Frequency detector

KW - Frequency multiplication

KW - Frequency synthesizer

KW - High speed

KW - Low jitter

KW - Low noise

KW - Phase detector

KW - Phase frequency detector (PFD)

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JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

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ER -

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

Abstract

Keywords

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