A 24 GHz PLL with Low Phase Noise for 60 GHz Sliding-IF Transceiver in a 65-nm CMOS

Yang Liu, Zhiqun Li, Hao Gao (Corresponding author)

Research output: Contribution to journalArticleAcademicpeer-review

Abstract

This work presents a 24 GHz integrated Phase-Locked Loop in a 60 GHz sliding-IF transceiver for IEEE 802.15.3c standard with low phase noise. For low phase noise, a varactor and MOM cap combination method is applied in this 24 GHz PLL. The capacitor bank is optimized to decrease the noise folding from circuit noise to phase noise within this method. This analog PLL is fabricated in a 65 nm CMOS technology with a phase noise of −98.8 dBc/Hz@1MHz, and the reference spur is −62.4 dBc. The power consumption of the PLL is 45.6 mW, including the output buffer.
Original languageEnglish
Article number105106
Number of pages7
JournalMicroelectronics Journal
Volume113
DOIs
Publication statusAccepted/In press - 7 May 2021

Keywords

  • CMOS
  • Divider
  • PLL
  • Phase noise
  • VCO

Fingerprint Dive into the research topics of 'A 24 GHz PLL with Low Phase Noise for 60 GHz Sliding-IF Transceiver in a 65-nm CMOS'. Together they form a unique fingerprint.

Cite this