A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW

Lucien Breems, Muhammed Bolatkale, Hans Brekelmans, Shagun Bajoria, Jan Niehof, Robert Rutten, Bert Oude-Essink, Franco Fritschij, Jagdip Singh, Gerard Lassche

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

8 Citations (Scopus)

Abstract

The trend towards wideband radio front-ends (RFE) for car radio receivers allows for digital tuning and channel filtering, simultaneous reception of multiple channels and reduced interference. A filter-less RFE requires a high dynamic range and very linear analog-to-digital converter (ADC). For AM/FM, typical total harmonic distortion (THD), intermodulation distortion and spurious tone levels of the ADC must be below -100dBc. These nonlinearity levels are much lower than the required ADC noise that is necessary to maintain high reception quality of a weak wanted signal in the presence of strong unfiltered interferers. Such audio-like linearity performance has been demonstrated for low input signal frequencies up to several hundreds of kHz [1-2], but the spurious free dynamic range (SFDR) of ADCs with >10MHz bandwidth is typically limited to 80 to 90dB [3-4] due to static mismatches associated with multi-bit quantization and dynamic errors such as data-dependent disturbances on the DAC supply [1]. This paper presents a continuous-time (CT) ΔΣ ADC that achieves -102dB THD, -104dB IM3, >110dB SFDR and 77dB SNDR in 25MHz bandwidth over process, voltage and temperature (PVT) variations. Such high linearity is achieved by using a 1b feedback DAC, which is highly insensitive to process spread and mismatch, in combination with a wideband high-precision voltage regulator that is designed to mitigate dynamic errors of the 1b DAC.

Original languageEnglish
Title of host publication2016 IEEE International Solid-State Circuits Conference, ISSCC 2016
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages272-273
Number of pages2
ISBN (Electronic)9781467394666
DOIs
Publication statusPublished - 23 Feb 2016
Event63th IEEE International Solid- State Circuits Conference (ISSCC 2016) - San Francisco, United States
Duration: 31 Jan 20164 Feb 2016
Conference number: 63

Conference

Conference63th IEEE International Solid- State Circuits Conference (ISSCC 2016)
Abbreviated titleISSCC
CountryUnited States
CitySan Francisco
Period31/01/164/02/16

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    Breems, L., Bolatkale, M., Brekelmans, H., Bajoria, S., Niehof, J., Rutten, R., Oude-Essink, B., Fritschij, F., Singh, J., & Lassche, G. (2016). A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016 (pp. 272-273). [7418012] Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSCC.2016.7418012