A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction

P.J.A. Harpe; Eugenio Cantatore; Arthur Roermund, van

doi:10.1109/ISSCC.2013.6487730

A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction

P.J.A. Harpe, Eugenio Cantatore, Arthur Roermund, van

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

121 Citations (Scopus)

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Abstract

Low-power sensor applications e.g. for environmental monitoring, bio-potential recording, and wireless autonomous sensor networks require highly power-efficient ADCs, typically with resolutions of at least 10b. SAR ADCs are generally beneficial in terms of power efficiency. However, the most power-efficient designs currently lack the required accuracy for these applications [1, 2], as they are limited to 9b ENOB. Other designs that have sufficient accuracy (10b) are limited to power efficiencies above 10fJ/conv-step [3]. The aim of this work is to increase the accuracy of highly efficient SAR ADCs beyond 10b, while further improving the efficiency to 2.2fJ/conv-step. To do so, this work introduces a Data-Driven Noise-Reduction method to efficiently suppress comparator noise, applies a segmented capacitive DAC with 250aF unit elements for better efficiency and accuracy, and implements a self-oscillating comparator to locally generate the internally required oversampled clock.

Original language	English
Title of host publication	Proceedings of the 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 17-21 February 2013, San Francisco, California
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	270-271
ISBN (Print)	978-1-4673-4515-6
DOIs	https://doi.org/10.1109/ISSCC.2013.6487730
Publication status	Published - 2013
Event	60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, United States Duration: 17 Feb 2013 → 21 Feb 2013 Conference number: 60

Conference

Conference	60th IEEE International Solid-State Circuits Conference, ISSCC 2013
Abbreviated title	ISSCC 2013
Country/Territory	United States
City	San Francisco
Period	17/02/13 → 21/02/13
Other	“60 Years of (Em)Powering the Future”

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10.1109/ISSCC.2013.6487730

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Harpe, P. J. A., Cantatore, E., & Roermund, van, A. (2013). A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction. In Proceedings of the 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 17-21 February 2013, San Francisco, California (pp. 270-271). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISSCC.2013.6487730

Harpe, P.J.A. ; Cantatore, Eugenio ; Roermund, van, Arthur. / A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction. Proceedings of the 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 17-21 February 2013, San Francisco, California. Piscataway : Institute of Electrical and Electronics Engineers, 2013. pp. 270-271

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abstract = "Low-power sensor applications e.g. for environmental monitoring, bio-potential recording, and wireless autonomous sensor networks require highly power-efficient ADCs, typically with resolutions of at least 10b. SAR ADCs are generally beneficial in terms of power efficiency. However, the most power-efficient designs currently lack the required accuracy for these applications [1, 2], as they are limited to 9b ENOB. Other designs that have sufficient accuracy (10b) are limited to power efficiencies above 10fJ/conv-step [3]. The aim of this work is to increase the accuracy of highly efficient SAR ADCs beyond 10b, while further improving the efficiency to 2.2fJ/conv-step. To do so, this work introduces a Data-Driven Noise-Reduction method to efficiently suppress comparator noise, applies a segmented capacitive DAC with 250aF unit elements for better efficiency and accuracy, and implements a self-oscillating comparator to locally generate the internally required oversampled clock.",

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Harpe, PJA , Cantatore, E & Roermund, van, A 2013, A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction. in Proceedings of the 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 17-21 February 2013, San Francisco, California. Institute of Electrical and Electronics Engineers, Piscataway, pp. 270-271, 60th IEEE International Solid-State Circuits Conference, ISSCC 2013, San Francisco, California, United States, 17/02/13. https://doi.org/10.1109/ISSCC.2013.6487730

A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction. / Harpe, P.J.A.; Cantatore, Eugenio; Roermund, van, Arthur.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 17-21 February 2013, San Francisco, California. Piscataway: Institute of Electrical and Electronics Engineers, 2013. p. 270-271.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - Low-power sensor applications e.g. for environmental monitoring, bio-potential recording, and wireless autonomous sensor networks require highly power-efficient ADCs, typically with resolutions of at least 10b. SAR ADCs are generally beneficial in terms of power efficiency. However, the most power-efficient designs currently lack the required accuracy for these applications [1, 2], as they are limited to 9b ENOB. Other designs that have sufficient accuracy (10b) are limited to power efficiencies above 10fJ/conv-step [3]. The aim of this work is to increase the accuracy of highly efficient SAR ADCs beyond 10b, while further improving the efficiency to 2.2fJ/conv-step. To do so, this work introduces a Data-Driven Noise-Reduction method to efficiently suppress comparator noise, applies a segmented capacitive DAC with 250aF unit elements for better efficiency and accuracy, and implements a self-oscillating comparator to locally generate the internally required oversampled clock.

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Harpe PJA , Cantatore E, Roermund, van A. A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction. In Proceedings of the 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 17-21 February 2013, San Francisco, California. Piscataway: Institute of Electrical and Electronics Engineers. 2013. p. 270-271 doi: 10.1109/ISSCC.2013.6487730

A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction

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