A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction

P.J.A. Harpe, Eugenio Cantatore, Arthur Roermund, van

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

117 Citations (Scopus)
8 Downloads (Pure)


Low-power sensor applications e.g. for environmental monitoring, bio-potential recording, and wireless autonomous sensor networks require highly power-efficient ADCs, typically with resolutions of at least 10b. SAR ADCs are generally beneficial in terms of power efficiency. However, the most power-efficient designs currently lack the required accuracy for these applications [1, 2], as they are limited to 9b ENOB. Other designs that have sufficient accuracy (10b) are limited to power efficiencies above 10fJ/conv-step [3]. The aim of this work is to increase the accuracy of highly efficient SAR ADCs beyond 10b, while further improving the efficiency to 2.2fJ/conv-step. To do so, this work introduces a Data-Driven Noise-Reduction method to efficiently suppress comparator noise, applies a segmented capacitive DAC with 250aF unit elements for better efficiency and accuracy, and implements a self-oscillating comparator to locally generate the internally required oversampled clock.
Original languageEnglish
Title of host publicationProceedings of the 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 17-21 February 2013, San Francisco, California
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)978-1-4673-4515-6
Publication statusPublished - 2013
Event60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, United States
Duration: 17 Feb 201321 Feb 2013
Conference number: 60


Conference60th IEEE International Solid-State Circuits Conference, ISSCC 2013
Abbreviated titleISSCC 2013
Country/TerritoryUnited States
CitySan Francisco
Other“60 Years of (Em)Powering the Future”


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