A 2.2 GHz continuous-time Δ Σ ADC With-102 dBc THD and 25 MHz bandwidth

Lucien Breems; Muhammed Bolatkale; Hans Brekelmans; Shagun Bajoria; Jan Niehof; Robert Rutten; Bert Oude-Essink; Franco Fritschij; Jagdip Singh; Gerard Lassche

doi:10.1109/JSSC.2016.2591826

A 2.2 GHz continuous-time Δ Σ ADC With-102 dBc THD and 25 MHz bandwidth

Lucien Breems, Muhammed Bolatkale, Hans Brekelmans, Shagun Bajoria, Jan Niehof, Robert Rutten, Bert Oude-Essink, Franco Fritschij, Jagdip Singh, Gerard Lassche

Integrated Circuits

Research output: Contribution to journal › Article › Academic › peer-review

18 Citations (Scopus)

Abstract

This paper presents a 2.2 GHz continuous-time Δ Σ ADC that achieves-102 dBc THD and 77 dB SNDR in 25 MHz bandwidth over process, voltage, and temperature (PVT) variations. Measured second-order intermodulation distortion (IM₂) and the third-order intermodulation distortion (IM₃) are-115 dBc and-114 dBc, respectively. The modulator comprises a 4th-order loop filter with inverter-based single-opamp resonators, a 1-bit quantizer with dither circuitry and ELD compensation and 1-bit feedback DACs that are highly insensitive to process spread and mismatch. The 1-bit DAC incorporates a wideband high precision series-shunt voltage regulator to mitigate dynamic errors associated with DAC switching. The ADC was fabricated in TSMC 65 nm CMOS and the active die area including the regulators is 0.6 mm². The total power consumption of the 1.2 V supplied modulator core is 41.4 mW.

Original language	English
Article number	7543462
Pages (from-to)	2906-2916
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	51
Issue number	12
DOIs	https://doi.org/10.1109/JSSC.2016.2591826
Publication status	Published - 1 Dec 2016

Keywords

Analog-to-digital conversion
continuous-time
delta-sigma
oversampling ADCs
radio receiver
voltage regulator

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10.1109/JSSC.2016.2591826

Cite this

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title = "A 2.2 GHz continuous-time Δ Σ ADC With-102 dBc THD and 25 MHz bandwidth",

abstract = "This paper presents a 2.2 GHz continuous-time Δ Σ ADC that achieves-102 dBc THD and 77 dB SNDR in 25 MHz bandwidth over process, voltage, and temperature (PVT) variations. Measured second-order intermodulation distortion (IM2) and the third-order intermodulation distortion (IM3) are-115 dBc and-114 dBc, respectively. The modulator comprises a 4th-order loop filter with inverter-based single-opamp resonators, a 1-bit quantizer with dither circuitry and ELD compensation and 1-bit feedback DACs that are highly insensitive to process spread and mismatch. The 1-bit DAC incorporates a wideband high precision series-shunt voltage regulator to mitigate dynamic errors associated with DAC switching. The ADC was fabricated in TSMC 65 nm CMOS and the active die area including the regulators is 0.6 mm2. The total power consumption of the 1.2 V supplied modulator core is 41.4 mW.",

keywords = "Analog-to-digital conversion, continuous-time, delta-sigma, oversampling ADCs, radio receiver, voltage regulator",

author = "Lucien Breems and Muhammed Bolatkale and Hans Brekelmans and Shagun Bajoria and Jan Niehof and Robert Rutten and Bert Oude-Essink and Franco Fritschij and Jagdip Singh and Gerard Lassche",

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A 2.2 GHz continuous-time Δ Σ ADC With-102 dBc THD and 25 MHz bandwidth. / Breems, Lucien; Bolatkale, Muhammed; Brekelmans, Hans; Bajoria, Shagun; Niehof, Jan; Rutten, Robert; Oude-Essink, Bert; Fritschij, Franco; Singh, Jagdip; Lassche, Gerard.

In: IEEE Journal of Solid-State Circuits, Vol. 51, No. 12, 7543462, 01.12.2016, p. 2906-2916.

Research output: Contribution to journal › Article › Academic › peer-review

TY - JOUR

T1 - A 2.2 GHz continuous-time Δ Σ ADC With-102 dBc THD and 25 MHz bandwidth

AU - Breems, Lucien

AU - Bolatkale, Muhammed

AU - Brekelmans, Hans

AU - Bajoria, Shagun

AU - Niehof, Jan

AU - Rutten, Robert

AU - Oude-Essink, Bert

AU - Fritschij, Franco

AU - Singh, Jagdip

AU - Lassche, Gerard

PY - 2016/12/1

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N2 - This paper presents a 2.2 GHz continuous-time Δ Σ ADC that achieves-102 dBc THD and 77 dB SNDR in 25 MHz bandwidth over process, voltage, and temperature (PVT) variations. Measured second-order intermodulation distortion (IM2) and the third-order intermodulation distortion (IM3) are-115 dBc and-114 dBc, respectively. The modulator comprises a 4th-order loop filter with inverter-based single-opamp resonators, a 1-bit quantizer with dither circuitry and ELD compensation and 1-bit feedback DACs that are highly insensitive to process spread and mismatch. The 1-bit DAC incorporates a wideband high precision series-shunt voltage regulator to mitigate dynamic errors associated with DAC switching. The ADC was fabricated in TSMC 65 nm CMOS and the active die area including the regulators is 0.6 mm2. The total power consumption of the 1.2 V supplied modulator core is 41.4 mW.

AB - This paper presents a 2.2 GHz continuous-time Δ Σ ADC that achieves-102 dBc THD and 77 dB SNDR in 25 MHz bandwidth over process, voltage, and temperature (PVT) variations. Measured second-order intermodulation distortion (IM2) and the third-order intermodulation distortion (IM3) are-115 dBc and-114 dBc, respectively. The modulator comprises a 4th-order loop filter with inverter-based single-opamp resonators, a 1-bit quantizer with dither circuitry and ELD compensation and 1-bit feedback DACs that are highly insensitive to process spread and mismatch. The 1-bit DAC incorporates a wideband high precision series-shunt voltage regulator to mitigate dynamic errors associated with DAC switching. The ADC was fabricated in TSMC 65 nm CMOS and the active die area including the regulators is 0.6 mm2. The total power consumption of the 1.2 V supplied modulator core is 41.4 mW.

KW - Analog-to-digital conversion

KW - continuous-time

KW - delta-sigma

KW - oversampling ADCs

KW - radio receiver

KW - voltage regulator

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A 2.2 GHz continuous-time Δ Σ ADC With-102 dBc THD and 25 MHz bandwidth

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