This paper presents a 2.2 GHz continuous-time Δ Σ ADC that achieves-102 dBc THD and 77 dB SNDR in 25 MHz bandwidth over process, voltage, and temperature (PVT) variations. Measured second-order intermodulation distortion (IM2) and the third-order intermodulation distortion (IM3) are-115 dBc and-114 dBc, respectively. The modulator comprises a 4th-order loop filter with inverter-based single-opamp resonators, a 1-bit quantizer with dither circuitry and ELD compensation and 1-bit feedback DACs that are highly insensitive to process spread and mismatch. The 1-bit DAC incorporates a wideband high precision series-shunt voltage regulator to mitigate dynamic errors associated with DAC switching. The ADC was fabricated in TSMC 65 nm CMOS and the active die area including the regulators is 0.6 mm2. The total power consumption of the 1.2 V supplied modulator core is 41.4 mW.
|Number of pages||11|
|Journal||IEEE Journal of Solid-State Circuits|
|Publication status||Published - 1 Dec 2016|
- Analog-to-digital conversion
- oversampling ADCs
- radio receiver
- voltage regulator