A 2 GS/s, 6-bit DAC for UWB applications in 0.18 μm CMOS technology

Yi Zhang; Zhonghua Liu; Changchun Zhang; Yufeng Guo; Ying Zhang; Xiaopeng Li; Youtao Zhang; Hao Gao

doi:10.5573/JSTS.2019.19.6.517

A 2 GS/s, 6-bit DAC for UWB applications in 0.18 μm CMOS technology

Yi Zhang (Corresponding author)
, Zhonghua Liu
, Changchun Zhang
, Yufeng Guo
, Ying Zhang
, Xiaopeng Li
, Youtao Zhang
, Hao Gao

Research output: Contribution to journal › Article › Academic › peer-review

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Abstract

To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra-wideband (UWB) applications, is presented. The DAC is based on current steering architecture and is segmented with 4 bit unary and 2 bit binary. To realize larger linear range and fast switching, the source degeneration switch is designed instead of the traditional differential switch. The DAC is designed and taped-out in SMIC 0.18 μm CMOS technology and the area is 975 μm☓₇₇₅ μm. The wafer bonding measurement results shows that the DNL is 0.11 LSB, INL is 0.25 LSB. Under a clock frequency of 2 GHz, the DAC can achieve a SFDR of 51 dB for input signal of 6MHz, and a SFDR of 32.4 dB for Nyquist input while the power consumption is 79 mW.

Original language	English
Pages (from-to)	517-526
Number of pages	10
Journal	Journal of Semiconductor Technology and Science
Volume	19
Issue number	6
DOIs	https://doi.org/10.5573/JSTS.2019.19.6.517
Publication status	Published - Dec 2019

Funding

The research is supported by National Natural Science Found (No. 61804081, 61828401), China Postdoctoral Science Foundation (No. 2018M642292), Open project of State Key Laboratory of Millimeter Waves (No. K201727), Open project of National and Local Joint Engineering Laboratory of RF Integration and Micro-assembly Technology (No. KFJJ20170203) and Scientific Research Foundation of Nanjing University of Posts and Telecommunications (NUPTSF No. NY215138).

Keywords

CMOS
DAC
Segmented current steering
UWB
segmented current steering

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@article{94b13ddd44724508ad7916e31be3b516,

title = "A 2 GS/s, 6-bit DAC for UWB applications in 0.18 μm CMOS technology",

abstract = "To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra-wideband (UWB) applications, is presented. The DAC is based on current steering architecture and is segmented with 4 bit unary and 2 bit binary. To realize larger linear range and fast switching, the source degeneration switch is designed instead of the traditional differential switch. The DAC is designed and taped-out in SMIC 0.18 μm CMOS technology and the area is 975 μm☓775 μm. The wafer bonding measurement results shows that the DNL is 0.11 LSB, INL is 0.25 LSB. Under a clock frequency of 2 GHz, the DAC can achieve a SFDR of 51 dB for input signal of 6MHz, and a SFDR of 32.4 dB for Nyquist input while the power consumption is 79 mW.",

keywords = "CMOS, DAC, Segmented current steering, UWB, segmented current steering",

author = "Yi Zhang and Zhonghua Liu and Changchun Zhang and Yufeng Guo and Ying Zhang and Xiaopeng Li and Youtao Zhang and Hao Gao",

year = "2019",

month = dec,

doi = "10.5573/JSTS.2019.19.6.517",

language = "English",

volume = "19",

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T1 - A 2 GS/s, 6-bit DAC for UWB applications in 0.18 μm CMOS technology

AU - Zhang, Yi

AU - Liu, Zhonghua

AU - Zhang, Changchun

AU - Guo, Yufeng

AU - Zhang, Ying

AU - Li, Xiaopeng

AU - Zhang, Youtao

AU - Gao, Hao

PY - 2019/12

Y1 - 2019/12

N2 - To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra-wideband (UWB) applications, is presented. The DAC is based on current steering architecture and is segmented with 4 bit unary and 2 bit binary. To realize larger linear range and fast switching, the source degeneration switch is designed instead of the traditional differential switch. The DAC is designed and taped-out in SMIC 0.18 μm CMOS technology and the area is 975 μm☓775 μm. The wafer bonding measurement results shows that the DNL is 0.11 LSB, INL is 0.25 LSB. Under a clock frequency of 2 GHz, the DAC can achieve a SFDR of 51 dB for input signal of 6MHz, and a SFDR of 32.4 dB for Nyquist input while the power consumption is 79 mW.

AB - To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra-wideband (UWB) applications, is presented. The DAC is based on current steering architecture and is segmented with 4 bit unary and 2 bit binary. To realize larger linear range and fast switching, the source degeneration switch is designed instead of the traditional differential switch. The DAC is designed and taped-out in SMIC 0.18 μm CMOS technology and the area is 975 μm☓775 μm. The wafer bonding measurement results shows that the DNL is 0.11 LSB, INL is 0.25 LSB. Under a clock frequency of 2 GHz, the DAC can achieve a SFDR of 51 dB for input signal of 6MHz, and a SFDR of 32.4 dB for Nyquist input while the power consumption is 79 mW.

KW - CMOS

KW - DAC

KW - Segmented current steering

KW - UWB

KW - segmented current steering

UR - https://www.scopus.com/pages/publications/85077288310

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DO - 10.5573/JSTS.2019.19.6.517

M3 - Article

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SN - 1598-1657

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JO - Journal of Semiconductor Technology and Science

JF - Journal of Semiconductor Technology and Science

IS - 6

ER -

A 2 GS/s, 6-bit DAC for UWB applications in 0.18 μm CMOS technology

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