TY - JOUR
T1 - A 2 GS/s, 6-bit DAC for UWB applications in 0.18 μm CMOS technology
AU - Zhang, Yi
AU - Liu, Zhonghua
AU - Zhang, Changchun
AU - Guo, Yufeng
AU - Zhang, Ying
AU - Li, Xiaopeng
AU - Zhang, Youtao
AU - Gao, Hao
PY - 2019/12
Y1 - 2019/12
N2 - To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra-wideband (UWB) applications, is presented. The DAC is based on current steering architecture and is segmented with 4 bit unary and 2 bit binary. To realize larger linear range and fast switching, the source degeneration switch is designed instead of the traditional differential switch. The DAC is designed and taped-out in SMIC 0.18 μm CMOS technology and the area is 975 μm☓775 μm. The wafer bonding measurement results shows that the DNL is 0.11 LSB, INL is 0.25 LSB. Under a clock frequency of 2 GHz, the DAC can achieve a SFDR of 51 dB for input signal of 6MHz, and a SFDR of 32.4 dB for Nyquist input while the power consumption is 79 mW.
AB - To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra-wideband (UWB) applications, is presented. The DAC is based on current steering architecture and is segmented with 4 bit unary and 2 bit binary. To realize larger linear range and fast switching, the source degeneration switch is designed instead of the traditional differential switch. The DAC is designed and taped-out in SMIC 0.18 μm CMOS technology and the area is 975 μm☓775 μm. The wafer bonding measurement results shows that the DNL is 0.11 LSB, INL is 0.25 LSB. Under a clock frequency of 2 GHz, the DAC can achieve a SFDR of 51 dB for input signal of 6MHz, and a SFDR of 32.4 dB for Nyquist input while the power consumption is 79 mW.
KW - CMOS
KW - DAC
KW - Segmented current steering
KW - UWB
KW - segmented current steering
UR - http://www.scopus.com/inward/record.url?scp=85077288310&partnerID=8YFLogxK
U2 - 10.5573/JSTS.2019.19.6.517
DO - 10.5573/JSTS.2019.19.6.517
M3 - Article
AN - SCOPUS:85077288310
VL - 19
SP - 517
EP - 526
JO - Journal of Semiconductor Technology and Science
JF - Journal of Semiconductor Technology and Science
SN - 1598-1657
IS - 6
ER -