A 2-µm CMOS 8-MIPS digital signal processor with parallel processing capability

A 2-µm CMOS VLSI digital signal processor (DSP) family, the SP50, capable of eight million instructions per second (8 MIPS) and up to six concurrent operations in each instruction, is described. Two DSP’s, the PCB5010 and PCB5011, have been developed. Both are based on a common architecture which contains two 16-bit data buses, and a 16×16 →40-bit multiplier accumulator and 16-bit ALU, both with multi-precision support in hardware. Also implemented are two static data RAM's (128×16 or 256×16 each), a data ROM (512 x 16), a 15-word three-port register file, three address computation units (ACU‘s), and five serial and parallel I/O interfaces. The data path is controlled by an orthogonal instruction set, using 40-bit microcode words. The controller contains a five-level stack and an instruction repeat register, and can have either on-chip program memory (RAM: 32 x 40; ROM: 987x 40) or off-chip program memory (up to 64K×40).). Benchmarks show a two to sixfold improvement in overall performance over its predecessors.