A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

LanguageEnglish
Title of host publication2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages5
ISBN (Electronic)978-1-5386-4881-0
ISBN (Print)978-1-5386-4882-7
DOIs
StatePublished - 26 Apr 2018
Event2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence Conference Center, Florence, Italy
Duration: 27 May 201830 May 2018
https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Conference

Conference2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
Abbreviated titleISCAS 2018
CountryItaly
CityFlorence
Period27/05/1830/05/18
Internet address

Fingerprint

Ultra-wideband (UWB)
Modulators
Bandwidth
Electric power utilization
Clock distribution networks
Transistors
Feedback

Keywords

  • Modulation
  • Power demand
  • Receivers
  • Thermal noise
  • Inverters
  • Bandwidth
  • Low-frequency noise

Cite this

Neofytou, M., Zhou, M., Bolatkale, M., Liu, Q., Zhang, C., Radulov, G., ... Breems, L. (2018). A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings [8351046] Piscataway: Institute of Electrical and Electronics Engineers. DOI: 10.1109/ISCAS.2018.8351046
Neofytou, M. ; Zhou, M. ; Bolatkale, M. ; Liu, Q. ; Zhang, C. ; Radulov, G. ; Baltus, P. ; Breems, L./ A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2018.
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Neofytou, M, Zhou, M, Bolatkale, M, Liu, Q, Zhang, C, Radulov, G, Baltus, P & Breems, L 2018, A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8351046, Institute of Electrical and Electronics Engineers, Piscataway, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018, Florence, Italy, 27/05/18. DOI: 10.1109/ISCAS.2018.8351046

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. / Neofytou, M.; Zhou, M.; Bolatkale, M.; Liu, Q.; Zhang, C.; Radulov, G.; Baltus, P.; Breems, L.

2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2018. 8351046.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AU - Neofytou,M.

AU - Zhou,M.

AU - Bolatkale,M.

AU - Liu,Q.

AU - Zhang,C.

AU - Radulov,G.

AU - Baltus,P.

AU - Breems,L.

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N2 - This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

AB - This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

KW - Modulation

KW - Power demand

KW - Receivers

KW - Thermal noise

KW - Inverters

KW - Bandwidth

KW - Low-frequency noise

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Neofytou M, Zhou M, Bolatkale M, Liu Q, Zhang C, Radulov G et al. A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers. 2018. 8351046. Available from, DOI: 10.1109/ISCAS.2018.8351046