A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications

M. Neofytou; M. Zhou; M. Bolatkale; Q. Liu; C. Zhang; G. Radulov; P. Baltus; L. Breems

doi:10.1109/ISCAS.2018.8351046

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications

M. Neofytou, M. Zhou, M. Bolatkale, Q. Liu, C. Zhang, G. Radulov, P. Baltus, L. Breems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

6 Citations (Scopus)

7 Downloads (Pure)

Abstract

This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4^th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

Original language	English
Title of host publication	2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	5
ISBN (Electronic)	978-1-5386-4881-0
ISBN (Print)	978-1-5386-4882-7
DOIs	https://doi.org/10.1109/ISCAS.2018.8351046
Publication status	Published - 26 Apr 2018
Event	2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018) - Florence Conference Center, Florence, Italy Duration: 27 May 2018 → 30 May 2018 https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Conference

Conference	2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018)
Abbreviated title	ISCAS 2018
Country/Territory	Italy
City	Florence
Period	27/05/18 → 30/05/18
Internet address	https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8334884

Keywords

Modulation
Power demand
Receivers
Thermal noise
Inverters
Bandwidth
Low-frequency noise

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10.1109/ISCAS.2018.8351046

Cite this

Neofytou, M., Zhou, M., Bolatkale, M., Liu, Q., Zhang, C., Radulov, G., Baltus, P., & Breems, L. (2018). A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. In 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings Article 8351046 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2018.8351046

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abstract = "This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.",

keywords = "Modulation, Power demand, Receivers, Thermal noise, Inverters, Bandwidth, Low-frequency noise",

author = "M. Neofytou and M. Zhou and M. Bolatkale and Q. Liu and C. Zhang and G. Radulov and P. Baltus and L. Breems",

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note = "2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018), ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

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Neofytou, M, Zhou, M, Bolatkale, M, Liu, Q, Zhang, C, Radulov, G , Baltus, P & Breems, L 2018, A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. in 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings., 8351046, Institute of Electrical and Electronics Engineers, Piscataway, 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy, 27/05/18. https://doi.org/10.1109/ISCAS.2018.8351046

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. / Neofytou, M.; Zhou, M.; Bolatkale, M. et al.
2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2018. 8351046.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications

AU - Neofytou, M.

AU - Zhou, M.

AU - Bolatkale, M.

AU - Liu, Q.

AU - Zhang, C.

AU - Radulov, G.

AU - Baltus, P.

AU - Breems, L.

PY - 2018/4/26

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N2 - This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

AB - This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

KW - Modulation

KW - Power demand

KW - Receivers

KW - Thermal noise

KW - Inverters

KW - Bandwidth

KW - Low-frequency noise

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BT - 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2018 IEEE International Symposium on Circuits and Systems (ISCAS 2018)

Y2 - 27 May 2018 through 30 May 2018

ER -

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications

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