Abstract
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the International Symposium on Circuits and Systems (ISCAS2014), 1-5 June 2014, Melbourne, Australia |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 321-324 |
| ISBN (Print) | 978-1-4799-3431-7 |
| DOIs | |
| Publication status | Published - 2014 |
| Event | 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014) - Melbourne, Australia Duration: 1 Jun 2014 → 5 Jun 2014 http://iscas2014.org/ |
Conference
| Conference | 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014) |
|---|---|
| Abbreviated title | ISCAS 2014 |
| Country | Australia |
| City | Melbourne |
| Period | 1/06/14 → 5/06/14 |
| Internet address |
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A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios. / Meuleman, G.; Harpe, P.J.A.; Huang, X.; Roermund, van, A.H.M.
Proceedings of the International Symposium on Circuits and Systems (ISCAS2014), 1-5 June 2014, Melbourne, Australia. Piscataway : Institute of Electrical and Electronics Engineers, 2014. p. 321-324.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios
AU - Meuleman, G.
AU - Harpe, P.J.A.
AU - Huang, X.
AU - Roermund, van, A.H.M.
PY - 2014
Y1 - 2014
N2 - This paper describes the design and implementation of a low power IF frequency synthesizer which can be used in 2-tone envelope detection radios [1]. The synthesizer is based on an All-Digital PLL (AD-PLL) architecture. By means of a system noise analysis, overall noise performance is optimized while maintaining low-power operation. A current controlled ring-oscillator is designed, optimized for low-power and low phase-noise. An integer and fractional phase quantiser (PQ) is designed, where the fractional PQ is co-integrated with the oscillator to save power. The DAC, which digitally controls the oscillator, is implemented by a `coarse' and `fine' DAC topology to reduce the resolution requirement. The `fine' DAC resolution is increased by a third-order Delta-Sigma Modulator (DSM) to alleviate matching problems while maintaining monotonicity and keeping the power consumption low. Current division of the `fine' DAC, using a highly-linear current-mirror, enables fine frequency tuning while keeping low bias currents. The chip, consisting of a current controlled oscillator, `coarse' and `fine' DAC and fractional part of the phase quantiser is implemented in a 90 nm CMOS technology. The AD-PLL operates from 10 to 20 MHz and the power consumption (excluding digital loop filter and DSM) is only 19 µW at 20 MHz operation.
AB - This paper describes the design and implementation of a low power IF frequency synthesizer which can be used in 2-tone envelope detection radios [1]. The synthesizer is based on an All-Digital PLL (AD-PLL) architecture. By means of a system noise analysis, overall noise performance is optimized while maintaining low-power operation. A current controlled ring-oscillator is designed, optimized for low-power and low phase-noise. An integer and fractional phase quantiser (PQ) is designed, where the fractional PQ is co-integrated with the oscillator to save power. The DAC, which digitally controls the oscillator, is implemented by a `coarse' and `fine' DAC topology to reduce the resolution requirement. The `fine' DAC resolution is increased by a third-order Delta-Sigma Modulator (DSM) to alleviate matching problems while maintaining monotonicity and keeping the power consumption low. Current division of the `fine' DAC, using a highly-linear current-mirror, enables fine frequency tuning while keeping low bias currents. The chip, consisting of a current controlled oscillator, `coarse' and `fine' DAC and fractional part of the phase quantiser is implemented in a 90 nm CMOS technology. The AD-PLL operates from 10 to 20 MHz and the power consumption (excluding digital loop filter and DSM) is only 19 µW at 20 MHz operation.
U2 - 10.1109/ISCAS.2014.6865130
DO - 10.1109/ISCAS.2014.6865130
M3 - Conference contribution
SN - 978-1-4799-3431-7
SP - 321
EP - 324
BT - Proceedings of the International Symposium on Circuits and Systems (ISCAS2014), 1-5 June 2014, Melbourne, Australia
PB - Institute of Electrical and Electronics Engineers
CY - Piscataway
ER -