A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios

G. Meuleman, P.J.A. Harpe, X. Huang, A.H.M. Roermund, van

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Abstract

This paper describes the design and implementation of a low power IF frequency synthesizer which can be used in 2-tone envelope detection radios [1]. The synthesizer is based on an All-Digital PLL (AD-PLL) architecture. By means of a system noise analysis, overall noise performance is optimized while maintaining low-power operation. A current controlled ring-oscillator is designed, optimized for low-power and low phase-noise. An integer and fractional phase quantiser (PQ) is designed, where the fractional PQ is co-integrated with the oscillator to save power. The DAC, which digitally controls the oscillator, is implemented by a `coarse' and `fine' DAC topology to reduce the resolution requirement. The `fine' DAC resolution is increased by a third-order Delta-Sigma Modulator (DSM) to alleviate matching problems while maintaining monotonicity and keeping the power consumption low. Current division of the `fine' DAC, using a highly-linear current-mirror, enables fine frequency tuning while keeping low bias currents. The chip, consisting of a current controlled oscillator, `coarse' and `fine' DAC and fractional part of the phase quantiser is implemented in a 90 nm CMOS technology. The AD-PLL operates from 10 to 20 MHz and the power consumption (excluding digital loop filter and DSM) is only 19 µW at 20 MHz operation.
Original languageEnglish
Title of host publicationProceedings of the International Symposium on Circuits and Systems (ISCAS2014), 1-5 June 2014, Melbourne, Australia
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages321-324
ISBN (Print)978-1-4799-3431-7
DOIs
Publication statusPublished - 2014
Event2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014) - Melbourne, Australia
Duration: 1 Jun 20145 Jun 2014
http://iscas2014.org/

Conference

Conference2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014)
Abbreviated titleISCAS 2014
CountryAustralia
CityMelbourne
Period1/06/145/06/14
Internet address

Fingerprint

Radio receivers
Phase locked loops
Modulators
Electric power utilization
Frequency synthesizers
Bias currents
Phase noise
Mirrors
Tuning
Topology

Cite this

Meuleman, G., Harpe, P. J. A., Huang, X., & Roermund, van, A. H. M. (2014). A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios. In Proceedings of the International Symposium on Circuits and Systems (ISCAS2014), 1-5 June 2014, Melbourne, Australia (pp. 321-324). Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2014.6865130
Meuleman, G. ; Harpe, P.J.A. ; Huang, X. ; Roermund, van, A.H.M. / A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios. Proceedings of the International Symposium on Circuits and Systems (ISCAS2014), 1-5 June 2014, Melbourne, Australia. Piscataway : Institute of Electrical and Electronics Engineers, 2014. pp. 321-324
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abstract = "This paper describes the design and implementation of a low power IF frequency synthesizer which can be used in 2-tone envelope detection radios [1]. The synthesizer is based on an All-Digital PLL (AD-PLL) architecture. By means of a system noise analysis, overall noise performance is optimized while maintaining low-power operation. A current controlled ring-oscillator is designed, optimized for low-power and low phase-noise. An integer and fractional phase quantiser (PQ) is designed, where the fractional PQ is co-integrated with the oscillator to save power. The DAC, which digitally controls the oscillator, is implemented by a `coarse' and `fine' DAC topology to reduce the resolution requirement. The `fine' DAC resolution is increased by a third-order Delta-Sigma Modulator (DSM) to alleviate matching problems while maintaining monotonicity and keeping the power consumption low. Current division of the `fine' DAC, using a highly-linear current-mirror, enables fine frequency tuning while keeping low bias currents. The chip, consisting of a current controlled oscillator, `coarse' and `fine' DAC and fractional part of the phase quantiser is implemented in a 90 nm CMOS technology. The AD-PLL operates from 10 to 20 MHz and the power consumption (excluding digital loop filter and DSM) is only 19 µW at 20 MHz operation.",
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Meuleman, G, Harpe, PJA, Huang, X & Roermund, van, AHM 2014, A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios. in Proceedings of the International Symposium on Circuits and Systems (ISCAS2014), 1-5 June 2014, Melbourne, Australia. Institute of Electrical and Electronics Engineers, Piscataway, pp. 321-324, 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, Australia, 1/06/14. https://doi.org/10.1109/ISCAS.2014.6865130

A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios. / Meuleman, G.; Harpe, P.J.A.; Huang, X.; Roermund, van, A.H.M.

Proceedings of the International Symposium on Circuits and Systems (ISCAS2014), 1-5 June 2014, Melbourne, Australia. Piscataway : Institute of Electrical and Electronics Engineers, 2014. p. 321-324.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AB - This paper describes the design and implementation of a low power IF frequency synthesizer which can be used in 2-tone envelope detection radios [1]. The synthesizer is based on an All-Digital PLL (AD-PLL) architecture. By means of a system noise analysis, overall noise performance is optimized while maintaining low-power operation. A current controlled ring-oscillator is designed, optimized for low-power and low phase-noise. An integer and fractional phase quantiser (PQ) is designed, where the fractional PQ is co-integrated with the oscillator to save power. The DAC, which digitally controls the oscillator, is implemented by a `coarse' and `fine' DAC topology to reduce the resolution requirement. The `fine' DAC resolution is increased by a third-order Delta-Sigma Modulator (DSM) to alleviate matching problems while maintaining monotonicity and keeping the power consumption low. Current division of the `fine' DAC, using a highly-linear current-mirror, enables fine frequency tuning while keeping low bias currents. The chip, consisting of a current controlled oscillator, `coarse' and `fine' DAC and fractional part of the phase quantiser is implemented in a 90 nm CMOS technology. The AD-PLL operates from 10 to 20 MHz and the power consumption (excluding digital loop filter and DSM) is only 19 µW at 20 MHz operation.

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BT - Proceedings of the International Symposium on Circuits and Systems (ISCAS2014), 1-5 June 2014, Melbourne, Australia

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Meuleman G, Harpe PJA, Huang X, Roermund, van AHM. A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios. In Proceedings of the International Symposium on Circuits and Systems (ISCAS2014), 1-5 June 2014, Melbourne, Australia. Piscataway: Institute of Electrical and Electronics Engineers. 2014. p. 321-324 https://doi.org/10.1109/ISCAS.2014.6865130